Vertical metal/insulation layer/metal mim capacitor and manufacturing method thereof
A technology of insulating layer and metal layer, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as increasing cost and increasing chip area
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Embodiment 1
[0040] The manufacturing method of the vertical MIM capacitor includes the following steps:
[0041] Step 1, see Figure 4 , and a certain lower metal layer 105 is formed on the upper end of the first insulating layer 101 . Wherein, part of the lower metal 105 is used for the lower end leads of the two sides of the vertical MIM capacitor.
[0042] Step 2, see Figure 5 , a second insulating layer 111 is formed on the upper end of the first insulating layer 101 and the upper end of a certain underlying metal 105 , and a hard mask layer 115 is deposited on the second insulating layer 111 . The thickness of the hard mask layer 115 is 1000 angstroms˜10000 angstroms.
[0043] Step 3, see Image 6 and forming an X-1 layer contact hole 106 above the X-1 layer metal layer 102 in the second insulating layer 111 .
[0044] Step 4, see Figure 7 , coat photoresist 108 above the second insulating layer 111 and in the contact hole 106 of the X-1 layer, and use photolithography to def...
Embodiment 2
[0054] The difference between this embodiment and the first embodiment is that, see Figure 16 As shown, normal lithography of the X-1 layer contact hole 106 is used, while leaving the position of the groove where the vertical MIM capacitor needs to be formed to be exposed. The width of the groove 110 is greater than the width of the contact hole of the layer, and then the groove 110 is formed by anisotropic dry etching, and the rest is the same as that of the first embodiment.
[0055] The first embodiment needs to add a layer of mask, while the second embodiment does not need to add any mask.
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