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Reordering technology for PCIE (Peripheral Component Interface Express) application layer interface

A reordering and application layer technology, applied in the field of reordering, can solve problems such as blocking, request packet blocking, and inefficiency

Active Publication Date: 2014-01-22
丁贤根
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The purpose of the present invention is to overcome the above-mentioned deficiencies, provide a kind of reordering technology for PCIE application layer interface, solve the problem caused by blocking in the existing solution, improve the working rate, and can solve the out-of-sequence problem of the packet
[0013] The purpose of the present invention is achieved like this: a kind of reordering technology that is used for PCIE application layer interface, the ID number of request packet (Internal TAG) is all converted into different Int TAG number request packets by intermediate identification position, solves prior art The problem of inefficiency caused by blocking subsequent request packets; ID number lookup table (ID-Int lut) and PCIE lookup table (Int-PCIE) lut stores the relationship between ID number and Int TAG and the relationship between Int TAG and PCIE TAG It is convenient to perform corresponding inverse transformation when receiving the completion packet, so as to ensure in-order reception

Method used

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  • Reordering technology for PCIE (Peripheral Component Interface Express) application layer interface
  • Reordering technology for PCIE (Peripheral Component Interface Express) application layer interface
  • Reordering technology for PCIE (Peripheral Component Interface Express) application layer interface

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Embodiment Construction

[0024] Such as figure 2 As shown, the present invention relates to a reordering technology for the PCIE application layer interface, which converts the ID numbers of the accepted request packets into Int TAGs starting from TAG0 in the order of receipt, and stores the conversion relationship in the search Table ID-Int lut, so when receiving the request packet with the same ID number, it will become a request packet with different Int TAG after TAG conversion, and send it in the order of TAG number. According to the value of the configured Max Payload Size, the request packet is divided into multiple PCIE request packets. According to the PCIE protocol, the TAG numbers of different request packets must be different, so the TAG numbers of multiple split PCIE request packets are sequentially converted into PCIE TAG starting from 0, and store the conversion relationship in the lookup table Int-PCIE lut. The received completion packet stores the completion packet with the same Int...

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Abstract

The invention relates to a reordering technology for a PCIE (Peripheral Component Interface Express) application layer interface. Received data and information to be stored are stored by using an external memory; flag bits (TAG numbers) of a packet before and after segmentation are recorded by using a lookup table (lut), and an internal TAG number is added to firstly convert all received request packet identification numbers (ID number) into different internal identification numbers (Internal TAG). Thus, the problems caused by blockage in the conventional scheme are completely solved, the working speed is improved, and the problem of disorder of packets can be solved.

Description

technical field [0001] The invention relates to a reordering technology for a PCIE application layer interface. Background technique [0002] With the increasing speed of computer operation, the third generation of computer I / O technology, that is, PCIE bus technology, has been proposed. Compared with the traditional PCI bus technology, PCIE has different degrees of performance improvement in terms of bandwidth, delay, and speed. [0003] The hard core of PCIE includes PCIE physical layer, PCIE data link layer and PCIE transaction layer. The PCIE transaction layer is responsible for sending and receiving packets and performing corresponding error detection. The PCIE transaction layer belongs to the highest layer of the hard core, and communicates with the application layer through a bus connection. [0004] Compared with the Advanced High Performance Bus (AHB) bus, the new Advanced Extensible Interface (AXI) bus protocol proposed by ARM has better performance. The AXI bus...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/861H04L29/10
Inventor 林谷雒莎李冰丁贤根
Owner 丁贤根
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