Implementation method for RAM arranged in FPGA in convolutional interleaving mode based on data block

Abstract

The invention discloses an implementation method for an RAM arranged in an FPGA in a convolutional interleaving mode based on a data block. The implementation method includes the steps of firstly, setting an RAM storage area with the length larger than or equal to two times the length of the data block as an interleaving RAM; secondly, dividing the interleaving RAM into a high address interval and a low address interval according to addresses; thirdly, alternately accessing the data block in the high address interval of the interleaving RAM and the low address interval of the interleaving RAM, and beginning outputting a previous frame of interleaved data when beginning inputting a second frame of data, wherein the delay of input and output is the length of a frame of data. Convolutional interleaving of the data stream based on the RAM storage area is achieved, an access device occupied by interleaving is a continuous RAM interval, the alternate operation is achieved through the two RAM intervals which are continuous in space and separated in logic, the data delay produced due to interleaving is a signal frame period, and therefore continuous input and output can be achieved, the occupied FIFO resources are less, and the data delay is short.

Description

technical field [0001] The invention relates to the field of satellite mobile communication, in particular to a method for implementing data block-based convolution and interleaving in FPGA RAM. Background technique [0002] Due to the serious signal attenuation in the process of satellite broadcasting, the resulting transmission bit error rate is relatively high, and the transmission system is required to have a strong error protection capability. The error correction coding in the DVB-S transmission system adopts the inner and outer two layers of concatenated coding, with an interleaving scheme in the middle, which is realized in FPGA. [0003] When the interleaving depth I=12, as long as the input bit error rate is less than 2×10-4, the bit error rate after RS ​​decoding can reach 10-11, which is the level of "quasi-distortionless"; and when using infinite byte interleaving , as long as the input bit error rate is less than 7×10-4, the bit error rate after RS ​​decoding ...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a method for implementing data block-based convolutional interleaving in FPGA RAM to solve the problem that the existing interleaving method consumes a lot of FIFO resources and has a large data delay

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