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A charge compensation structure semiconductor wafer and its preparation method

A charge compensation and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, circuits, etc., can solve the problems affecting the shape of columnar semiconductor structures, affecting the withstand voltage characteristics and reliability of the chip, and achieve the improvement of reverse blocking of the chip Features and effects

Active Publication Date: 2017-02-15
北海惠科半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The manufacturing process of semiconductor wafers with such a charge compensation structure requires more anisotropic dry etching processes to control the distribution of columnar P-type semiconductors and N-type semiconductor regions, which easily affects the shape of the columnar semiconductor structure, thereby affecting the withstand voltage characteristics of the wafer. and reliability

Method used

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  • A charge compensation structure semiconductor wafer and its preparation method
  • A charge compensation structure semiconductor wafer and its preparation method

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Embodiment 1

[0015] figure 1 It is the first cross-sectional schematic diagram of a charge compensation structure semiconductor wafer of the present invention, combined below figure 1 The semiconductor device of the present invention will be described in detail.

[0016] A semiconductor wafer with a charge compensation structure, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E20cm -3 ; N-type semiconductor silicon material 2, located on the substrate layer 1, is an N-conduction type semiconductor silicon material with a thickness of 60 μm and a doping concentration of phosphorus atoms of 1E16cm -3 P-type semiconductor silicon material 3, located in N-type semiconductor silicon material 2, is a semiconductor silicon material of P conductivity type, with a width of 2 μm, a horizontal spacing of 2 μm, a vertical spacing of 3 μm, and a thickness of 27 μm above and below. The impurity con...

Embodiment 2

[0023] figure 2 It is the first cross-sectional schematic diagram of a charge compensation structure semiconductor wafer of the present invention, combined below figure 2 The semiconductor device of the present invention will be described in detail.

[0024] A semiconductor wafer with a charge compensation structure, comprising: a substrate layer 1, which is a semiconductor silicon material of N conductivity type, and the doping concentration of phosphorus atoms is 1E20cm -3 ; N-type semiconductor silicon material 2, located on the substrate layer 1, is an N-conduction type semiconductor silicon material with a thickness of 60 μm and a doping concentration of phosphorus atoms of 1E16cm -3 ; P-type semiconductor silicon material 3, located in N-type semiconductor silicon material 2, is a semiconductor silicon material of P conductivity type, with a width of 2 μm, a horizontal spacing of 2 μm, a vertical spacing of 3 μm, a thickness of 18 μm at the top, middle and bottom, bor...

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Abstract

The invention discloses a charge compensation structure semiconductor chip. A strip-shaped floating charge compensation structure is introduced to a semiconductor drift layer. After two or three times of epitaxy-etching technology, the charge compensation structure with a relatively high height-width ratio is formed in a vertical direction so that a reverse break-preventing characteristic of the chip is enhanced. The invention also provides a preparation method of the charge compensation structure semiconductor chip.

Description

technical field [0001] The invention relates to a charge compensation structure semiconductor wafer, and also relates to a preparation method of the charge compensation structure semiconductor wafer. Background technique [0002] The semiconductor wafer structure capable of achieving high withstand voltage and low on-resistance is a structure in which columnar P-type semiconductors and N-type semiconductor regions are alternately arranged side by side, and the columnar P-type semiconductors and N-type semiconductors are perpendicular to the wafer surface. By setting the impurity concentration and width of the P-type semiconductor and the N-type semiconductor to desired values, a high breakdown voltage can be realized when a reverse voltage drop is applied. Such a structure is called a charge compensation structure. [0003] Known charge compensation structure semiconductor wafer structure and manufacturing method are as follows: [0004] The first one is to deposit an N-ty...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/20
CPCH01L21/02365H01L29/0634
Inventor 朱江
Owner 北海惠科半导体科技有限公司