Cache Fault Tolerance Mechanism of Embedded Processor

Abstract

The invention discloses a cache fault-tolerant mechanism of an embedded processor. The cache fault-tolerant mechanism of the embedded processor includes the following steps that an instruction cache and a data cache are arranged in the embedded processor; the instruction cache comprises a reading port and a writing port; a parity check code is generated by the writing port according to data on a data bus when a cache is written; the data and the parity check code which are read from the cache are latched and meanwhile an access address of the cache to be read is latched by the reading port when the cache is read; a parity check code of the latched data is generated by the reading port and is in comparison with the parity check code which is read out by the reading port and no error is produced if the parity check codes are consistent; a cache error is produced if not; the data error is solved in an exception handling mode when the error is produced; the exception handling mode is executed. According to the cache fault-tolerant mechanism of the embedded processor, the error checking and the error handling are achieved through the parity check and the exception handling and accordingly the impact on the performance of circuits is small and increased hardware circuits are less.

Description

technical field [0001] The invention relates to a high-speed cache (Cache) fault-tolerant mechanism, in particular to a high-speed cache fault-tolerant mechanism of an embedded processor. Background technique [0002] A cache circuit is one of the main components of a computer processor and is mainly used to cache instructions and data. Usually, the caches for caching instructions and caching data are separated, called instruction caches and data caches, respectively. figure 1 Shows the location of the instruction cache and data cache on the processor datapath. The instruction cache is located on the instruction fetch data path; the data cache is located on the data access unit (load (load) / store (store) unit) data path. The instruction cache has two ports: a read port, connected to the instruction unit; a write port, connected to the bus interface unit. The data cache also has two ports, but both ports are readable and writable ports, one port is connected to the instruc...

AI Technical Summary

Problems solved by technology

The checking and error correction logic of ECC code is equivalent to the decoder with 8 inputs and 64 outputs, which is also a very complicated circuit

[0010] (2) The ECC protection mechanism increases the access time of the cache and reduces the performance of the processor

Figure 4 relative to the path image 3 There are more ECC code generation and ECC code checking and error correction logic in the path, resulting in an increase of more than 10% in the access time for accessing the cache

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