A multichannel ADC synchronization sampling intermediate frequency receiver

Abstract

The invention discloses a multichannel ADC synchronization sampling intermediate frequency receiver comprising a plurality of FPGA chips and DSP chips. The multichannel ADC synchronization sampling intermediate frequency receiver also comprises a first multichannel ADC module and a second multichannel ADC module. A signal output of the first multichannel ADC module is connected with a signal input of a first FPGA chip. Bidirectional multichannel data connection exists between the first FPGA chip and a first DSP chip. A signal output of a second multichannel ADC module is connected with a signal input of a second FPGA chip. Bidirectional multichannel data connection exists between the second FPGA chip and a second DSP chip. The first multichannel ADC module and the second multichannel ADC module are also connected with a clock distribution module. The multichannel ADC synchronization sampling intermediate frequency receiver is provided with a plurality of AD channels, and at the same time, sampling clocks are mutually independent. Synchronization acquisition can be carried out when an outer clock and an inner clock which are used in common. The multichannel ADC synchronization sampling intermediate frequency receiver is low in cost and high in cost performance. In addition, the multichannel ADC synchronization sampling intermediate frequency receiver can carry out Beidou and GPS satellite positioning, and is high in intelligentized degree.

Description

technical field [0001] The invention relates to a digital intermediate frequency receiver, in particular to a multi-channel ADC synchronous sampling intermediate frequency receiver. Background technique [0002] Existing IF digital receivers are mainly composed of a single analog-to-digital converter (ADC) and a digital down-converter. Convert the signal of interest to the baseband, and perform sampling rate conversion and filtering processing at the same time, and then send the orthogonal I and Q signals to the subsequent digital signal processor for baseband signal processing. In the entire IF receiver, the digital downconverter is The core of the entire IF digital receiver, but usually, the existing IF digital receiver can only realize single-channel signal sampling, with low working efficiency and single working mode. At the same time, when working on mobile vehicle-mounted equipment, various troubles often occur because of inability to locate satellites. [0003] Pate...

AI Technical Summary

Problems solved by technology

However, there is no internal and external clock distribution module, multi-channel ADC synchronous or asynchronous sampling, and any switching of internal and external clocks. At the same time, there is no satellite positioning function, which has positioning defects for IF receivers used on mobile devices.

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