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Techniques for wafer-level processing of QFN packages

A wafer-level packaging and wafer technology, applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc.

Active Publication Date: 2014-03-19
MAXIM INTEGRATED PROD INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Posts configured to provide interconnected electrical connections to integrated circuit chips

Method used

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  • Techniques for wafer-level processing of QFN packages
  • Techniques for wafer-level processing of QFN packages
  • Techniques for wafer-level processing of QFN packages

Examples

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Embodiment Construction

[0010] review

[0011] Devices using flat no-lead packaging technology such as QFN packaging technology provide good mechanical protection to the integrated circuit chip (die) contained in the device package by completely enclosing the integrated circuit chip in the package. However, flat no-lead (eg, QFN) packaged devices are very expensive to produce and typically offer relatively low pin counts (eg, QFN's pins are typically located along the wafer edge).

[0012] Wafer-level packaging is a chip-level packaging technique encompassing a variety of technologies whereby integrated circuit chips are packaged at the wafer level prior to singulation. Wafer-level packaging extends the wafer fabrication process to include device interconnection and device protection processes. Wafer-level packaging thus streamlines the process by allowing the wafer fabrication, packaging, testing, and burn-in processes to be integrated at the wafer level. Wafer-level packaging is generally less ...

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Abstract

Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Description

Background technique [0001] Flat no-lead packaging technologies, such as quad flat no-lead (QFN) packaging technology, physically and electrically connect the integrated circuit chip to the printed circuit board. Flat no-lead packaging technology typically uses a lead frame that includes an integrated circuit chip (die) mounted thereon. The wafer can be electrically interconnected with the lead frame by wire bonding or flip chip technology. A packaging structure is then formed on the lead frame to package the integrated circuit chip. Contents of the invention [0002] Techniques are described for fabricating wafer-level packaged semiconductor devices having a form factor similar to that of devices using flat-panel no-lead (eg, QFN) packaging technology. In one or more embodiments, a wafer level package device includes an integrated circuit chip (eg, a wafer) having at least one pillar (eg, a copper pillar) formed on the integrated circuit chip. The posts are configured to...

Claims

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Application Information

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IPC IPC(8): H01L23/498H01L23/48
CPCH01L2224/13111H01L24/17H01L2224/05647H01L24/06H01L25/0657H01L21/561H01L21/56H01L2224/0391H01L2224/05571H01L24/14H01L2224/0348H01L2224/02379H01L23/29H01L24/05H01L2224/05541H01L2224/11422H01L2224/05569H01L2224/0603H01L24/16H01L2224/94H01L24/11H01L2224/03903H01L24/13H01L2224/03462H01L23/3114H01L24/03H01L2224/05008H01L2225/06548H01L2224/16145H01L2225/06513H01L23/50H01L2924/00014H01L2224/0401H01L2224/03H01L2224/11H01L2924/00012H01L2924/01047H01L2924/01029H01L2224/05552H01L21/76877H01L23/28H01L23/481H01L2924/014
Inventor V·卡恩德卡尔K·坦比杜赖A·阿什拉夫扎德A·科尔卡H·D·阮
Owner MAXIM INTEGRATED PROD INC
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