Semiconductor package substrates having pillars and related methods
A technology of substrates and pillars, which is applied to semiconductor packaging substrates with pillars and related fields, and can solve problems such as lack of coplanarity and uneven current density distribution
Active Publication Date: 2014-03-26
ADVANCED SEMICON ENG INC
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Problems solved by technology
Lack of coplanarity can cause non-uniform current density distribution, which is especially severe on micro-scale patterns
Method used
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[0052] Please refer to figure 1 , which shows a cross-sectional view of a semiconductor package 100 according to one of the present embodiments. The semiconductor package 100 includes a substrate 102 , a die 104 and a package 106 .
[0053] The substrate 102 includes a first dielectric layer 108 , a first circuit pattern 110 , a plurality of pillars 112 , a second circuit pattern 114 , and a second dielectric layer 116 . The first circuit pattern 110 is electrically connected to the second circuit pattern 114 through a plurality of conductive vias 118 . Although the substrate 102 is shown to include only two layers of circuit patterns, in other embodiments, the substrate 102 may include any number of layers of circuit patterns, such as three or more layers.
[0054] The first dielectric layer 108 has a first dielectric surface 120 and a second dielectric surface 122 . The first dielectric surface 120 is opposite to the second dielectric surface 122 . For example, the first...
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Provided are semiconductor package substrates having pillars and related methods. The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.
Description
technical field [0001] The present embodiment relates to a semiconductor package substrate with pillars and related methods. Background technique [0002] Some semiconductor package substrates include pillars for connecting solder bumps of a semiconductor die to the substrate. After the reflow process, solder joints are formed between the die and the pillar, so that the die adheres to the pillar and secures the electrical connection therebetween. The pillars can be formed by electroplating. However, unpredictable and variable plating parameters in electroaqueous baths often result in over-plating or under-plating, which can cause the top surface of the plated cylinder to be non-coplanar. Lack of coplanarity can negatively affect the reliability of the solder joints after packaging. However, fine pitch solder bumps, wafer level packaging (WLP), and large substrates are particularly sensitive to this problem. The lack of coplanarity can cause non-uniform current density di...
Claims
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IPC IPC(8): H01L23/488H01L23/13H01L23/495H01L21/60
CPCH01L23/13H01L24/14H01L2224/13018H01L2224/81385H01L2221/68377H01L21/4853H01L2224/81193H01L2224/32225H01L23/495H01L2224/16235H01L2224/13147H01L2224/16225H01L21/6835H01L23/49816H01L23/488H01L2224/16238H01L2924/15311H01L2224/73204H01L24/48H01L2224/1401H01L24/13H01L2224/81815H01L24/32H01L2221/68359H01L2224/48H01L2224/81192H01L23/49822H01L2224/131H01L24/16H01L23/3128H01L2224/11462H01L2224/13017H01L23/49827H01L21/563H01L2924/00014H01L2924/12042H01L2924/181H05K3/007H05K3/4007H05K2201/0367H01L2924/00H01L2924/00012H01L2924/014H01L2224/45099H01L2224/45015H01L2924/207
Inventor 陈天赐陈光雄王圣民冯相铭郭燕桦
Owner ADVANCED SEMICON ENG INC