Unlock instant, AI-driven research and patent intelligence for your innovation.

Rapid modular reduction algorithm circuit for modular multiplication and modular squaring

A modular squaring and fast technology, applied in computing, electrical digital data processing, instruments, etc., can solve the problems of consuming modular reduction modules and modular reduction time, and achieve the effect of reducing time and reducing circuit area

Inactive Publication Date: 2014-04-02
XI AN JIAOTONG UNIV
View PDF6 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] At present, for the modular reduction process of large number modular multiplication and modular squaring, the usual solution is to calculate the results of multiplication and square first, and then use a special modular reduction circuit to perform the reduction. This solution requires a special modular reduction Simple Modules and Modular Reduced Time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Rapid modular reduction algorithm circuit for modular multiplication and modular squaring
  • Rapid modular reduction algorithm circuit for modular multiplication and modular squaring

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0012] Below in conjunction with accompanying drawing, the present invention is described in further detail:

[0013] see figure 1 and figure 2 , the present invention comprises the partial product generation circuit of multiplication or square, two input AND gate arrays of 2 m+1 bits, the full adder unit FA of m+2 bits and the scanning flip-flop of m+3 bits; 2 m+ The output terminal of the 1-bit two-input AND gate array is connected with a 4-2 compressor for compressing 4 multi-bit addends into 2 addends of m+1 bits, and the 4-2 compressor is m+1 bits The two-stage addition unit CSA. The four addends of the two-stage addition unit CSA come from: the partial product of the partial product generation circuit, the first m+1 bits of the sum of the scan flip-flops, and the output of two two-input AND gate arrays. One input end of the two-input AND gate array is respectively connected to the m+1th and m+2th output ends of the scan flip-flop, and the other input end is connected...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a rapid modular reduction algorithm circuit for modular multiplication and modular squaring. The circuit structurally comprises a multiplication or squaring partial product generation circuit, two (m+1)-order two-input AND gate arrays, m+1 two-grade CSA (Carry Save Adder) addition units, m+2 FA (Full Adder) units and m+3 scanning triggers. According to the rapid modular reduction algorithm circuit, a reduction method from a high order to a low order can be adopted for an m-order big prime number and the reduction can be carried out on a result when the multiplication and squaring operation is carried out, so that a reduction process which is independently carried out on multiplication and squaring results is avoided and the modular multiplication and modular squaring time is saved; meanwhile, a special modular reduction algorithm circuit module is saved and the circuit area is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a fast modular reduction algorithm circuit for modular multiplication and modular square. Background technique [0002] At present, for the modular reduction process of large number modular multiplication and modular squaring, the usual solution is to calculate the results of multiplication and square first, and then use a special modular reduction circuit to perform the reduction. This solution requires a special modular reduction Jane module and module reduce time. In view of this, it is necessary to design a new modular reduction algorithm, which can reduce the results while multiplying and squaring to solve the above problems. Contents of the invention [0003] The object of the present invention is to provide a kind of fast modular reduction algorithm circuit for modular multiplication and modular squaring, which can reduce the m-bit large prime number P from high...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/575
Inventor 雷绍充马璐钖魏晓彤
Owner XI AN JIAOTONG UNIV