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Array substrate, manufacturing method thereof, and display device

A technology for array substrates and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, instruments, etc., and can solve the problem of large gate off voltage delay, affecting the display effect of display devices, and pulling up gate off voltage, etc. problems, to achieve the effect of eliminating horizontal lines, improving display effects, and avoiding differences

Active Publication Date: 2016-08-17
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because multiple gate drive peripheral traces need to be arranged, the narrower gate drive peripheral traces have greater resistance, which makes the gate turn-off voltage delay larger. When the gate drive peripheral trace resistance is greater than about 200 ohms, in When the n+1th region performs gate scanning, the gate-off voltage of the nth region will be pulled up, resulting in a difference in the gate-off voltage at the junction of the nth region and the n+1th region, resulting in a junction There is a difference in brightness and darkness in the position, causing horizontal lines to appear on the display screen, which affects the display effect of the display device

Method used

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  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device

Examples

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Embodiment 1

[0061] Such as Figure 7 As shown, multiple Gate COF1s are arranged on the array substrate, and each Gate COF is connected to the DC circuit through the gate driving peripheral wiring VGL1, VGL2, VGL3, and VGL4. In this embodiment, connecting lines can be set on the Gate COF1 B. Connect the adjacent gate drive peripheral wiring through the connection line B on Gate COF1. The material of the connection line B can be metal to meet the low resistance requirement.

[0062] There is no strict requirement on the position of the connection line B, and it is better to keep the length of the connection line B as short as possible, so as to reduce the resistance of the connection line B as much as possible, so that the gate-off voltages of adjacent gate drive peripheral traces tend to be consistent.

Embodiment 2

[0064] Such as Figure 8 As shown, multiple Gate COF1s are arranged on the array substrate, and each Gate COF is connected to the DC circuit through the gate driving peripheral wiring VGL1, VGL2, VGL3 and VGL4. In this embodiment, the wiring area of ​​the array substrate can be A connection line A is provided, and the adjacent gate driving peripheral wiring is connected through the connection line A.

[0065] The connecting line A can be made on the same layer as the gate driving peripheral wiring 2, for example, both are made of a gate metal layer; further, the connecting line A can also be located in a different film layer from the gate driving peripheral wiring, and the connecting line A and the There is an insulating layer between the gate drive peripheral traces, and the connection line A and the gate drive peripheral traces are connected through via holes, so that there is no need to leave a space between the connection line A and the gate drive peripheral traces, and th...

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Abstract

Provided is an array substrate, comprising at least one DC circuit (12) to be connected to and provide gate shutdown voltage, and at least one gate drive peripheral line (VGL1, VGL2, VGL3, VGL4) to be connected to a gate drive circuit, adjacent gate drive peripheral lines being connected via connecting lines (51, 52, 53).

Description

technical field [0001] The present invention relates to the display field, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] Among the existing large-size liquid crystal panels, designs with narrow borders and high resolution are more and more popular. In a narrow bezel panel, the width of the gate drive peripheral traces decreases, while the length of the gate drive peripheral traces in a large-size panel increases, resulting in an increase in the resistance of the gate drive peripheral traces, and the gate (Gate) voltage The decrease in uniformity and the increase in the resistance of the gate drive peripheral wiring will also lead to a decrease in the stability of the gate turn-off voltage and an increase in delay. [0003] like figure 1 and figure 2 As shown, the gate off voltage in the existing panel is generated by the direct current (Direct Current, DCDC) circuit on the printed circuit board (P...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L21/77H01L23/538
CPCG02F1/13452H01L2924/0002
Inventor 董殿正黄海琴郑箫逸金炯旲
Owner BOE TECH GRP CO LTD