Semiconductor gate structure and method of forming same

Abstract

This invention discloses a semiconductor grid structure and a formation method for the same. The semiconductor grid structure possesses a trench which is constituted by a dielectric structure and a stacking structure. A first conductive layer can be conformally formed on the dielectric structure and the stacking structure. An oxide layer is formed along the first conductive layer and can be substantially removed from the first conductive layer. For some grid structures, a conductive filling structure possessing a first conductive layer and a second conductive layer can be deposited on the stacking structure and the dielectric structure.

Description

technical field [0001] The present invention relates to a structure of a semiconductor device and a method of forming the same, and more particularly, to a gate structure of a semiconductor device and a method of forming the gate structure of the semiconductor device. Background technique [0002] Shallow Trench Isolation ("STI") is a technique used in semiconductor devices to isolate adjacent transistors, especially in small isolation regions, such as sub-0.5 micron (sub-0.5 μm) isolation area, where a shallow trench is usually etched into the silicon material and one or more dielectric materials will be deposited in this trench, additional processing steps, such as chemical mechanical planarization, can be used to remove excess dielectric material . [0003] In particular, multiple masking, ion implantation, annealing, plasma etching, and chemical and physical vapor deposition steps can be used to form shallow trenches in shaded gate semiconductors. [0004] More specifi...

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Problems solved by technology

[0008] STI geometric differences and variations in STI size can lead to a large accumulation of various charges in the isolation oxide, making the semiconductor gate in operation react less than expected

During STI fabrication, it is difficult to precisely control the planarity and trench fill, for example, the trench oxide may be recessed below the active area of ​​the gate oxide, causing electric field spikes at the corner regions of the trench Mutations

[0009] The current conventional technique of controlling gate-to-drain capacitance using trench structures in metal-oxide semiconductors is a rather limited technique and will suffer due to the uneven thickness of the passivation layer and the uneven depth throughout the filled trench. aspect ratio, as well as other process factors, result in semiconductors with variable behavior

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