Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

How the transistor is formed

A technology of transistors and semiconductors, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as poor performance of transistors, and achieve the effect of preventing leakage current, preventing leakage current, and avoiding threshold voltage

Active Publication Date: 2016-06-29
SEMICON MFG INT (SHANGHAI) CORP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, the leakage current of the transistor with the stress layer formed in the prior art is relatively obvious, and the performance of the transistor is poor.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • How the transistor is formed
  • How the transistor is formed
  • How the transistor is formed

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0044] Figure 5 to Figure 9 It is a schematic cross-sectional structure diagram of the transistor formation process described in the first embodiment of the present invention, including:

[0045] Please refer to Figure 5 , providing a semiconductor substrate 200 with a gate structure 201 on the surface of the semiconductor substrate 200 .

[0046] The semiconductor substrate 200 is used to provide a working platform for subsequent processes, and the material of the semiconductor substrate 200 is single crystal silicon, or the semiconductor substrate 200 is a silicon-on-insulator (SOI) structure; in this embodiment, Since it is necessary to subsequently form a “Σ”-shaped opening with sidewalls and the surface of the semiconductor substrate 200 in the semiconductor substrate 200 , the crystal plane index of the surface of the semiconductor substrate 200 is (100).

[0047] The gate structure 201 includes: a gate dielectric layer 210 located on the surface of the semiconductor...

no. 2 example

[0075] Figure 10 to Figure 13 It is a schematic cross-sectional structure diagram of the transistor formation process described in the second embodiment of the present invention, including:

[0076] Please refer to Figure 10 , providing a semiconductor substrate 300, the surface of the semiconductor substrate 300 has a gate structure 301; using the gate structure 301 as a mask, forming openings 302 in the semiconductor substrate 300 on both sides of the gate structure 301.

[0077] The semiconductor substrate 300 is used to provide a working platform for subsequent processes, and the material of the semiconductor substrate 300 is single crystal silicon, or the semiconductor substrate 300 is a silicon-on-insulator (SOI) structure; in this embodiment, Since it is necessary to form a “Σ”-shaped opening with sidewalls and the surface of the semiconductor substrate 300 in the semiconductor substrate 300 later, the crystal plane index of the surface of the semiconductor substrate...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a forming method of a transistor. The forming method comprises the following steps that: a semiconductor substrate is provided, wherein the semiconductor substrate has a gate structure; openings are formed in the portions, at the two sides of the gate structure, of the semiconductor substrate; doping material layers are formed at the bottom surfaces and parts of side wall surfaces, approaching the bottoms, of the openings and parts of side wall surfaces of the openings are exposed by the doping material layers, wherein the parts of side wall surfaces approach the semiconductor substrate surface and doped ions are contained in the doping material layers; thermal annealing is carried out on the doping material layers and thus the doped ions in the doping material layers are diffused into the semiconductor substrate from the bottoms of the openings and the parts of side wall surfaces approaching the bottoms, and doping layers are formed at the surfaces of the semiconductor substrate covered by the doping material layers in the openings; after the thermal annealing process, the rest of doping material layers is removed; and after the removing of the rest of doping material layers, stress layers are formed in the openings. The formed transistor has the good performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] As the most basic semiconductor device, transistors are currently being widely used. With the increase of component density and integration of semiconductor devices, the gate size of transistors has become shorter than before; however, the shortened gate size of transistors will make transistors The short channel effect is generated, and then leakage current is generated, which finally affects the electrical performance of the semiconductor device. At present, in the prior art, the stress of the channel region of the transistor is mainly increased to increase the mobility of carriers, thereby increasing the driving current of the transistor and reducing the leakage current in the transistor. [0003] In the prior art, the method for increasing the stress of the channel region of the transistor i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336
CPCH01L29/165H01L29/6656H01L29/66636H01L29/7848
Inventor 隋运奇李凤莲
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products