Chip testing data transmission method based on dual-run-length alternative coding

A data transmission method and chip testing technology, applied in the field of system chip test data processing, can solve the problems of high test cost, small decoding circuit overhead, long decoding time, etc., achieve the effect of wide program adaptability and reduce chip overhead

Active Publication Date: 2014-04-23
SHANGHAI TAIYU INFORMATION TECH
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  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

The run-length-based coding scheme has a high data compression rate and a small decoding circuit overhead, Golomb [1] Encoding, FDR [2] Encoding and AFR [3] Encoding and so on are all run-based encoding schemes, but the above schemes still have the defects of low compression efficiency, responsible encoding, long decoding time, and high testing cost

Method used

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  • Chip testing data transmission method based on dual-run-length alternative coding
  • Chip testing data transmission method based on dual-run-length alternative coding
  • Chip testing data transmission method based on dual-run-length alternative coding

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Embodiment Construction

[0039] The present invention will be further described below in conjunction with the accompanying drawings.

[0040] Such as figure 1 , figure 2 , image 3 It can be seen that the chip test data transmission method based on double-run alternate coding of the present invention comprises the following steps:

[0041] A. If figure 1 It can be seen that the encoding steps include:

[0042] (1) Initialize the flag bit flag, which corresponds to an expected run length type; and record the initial value of the flag as f; the purpose of recording the initial value of the flag as f is to provide the first run length type reference for the subsequent decoding process.

[0043] (2) read the test data coding set bit by bit, obtain the current run length, and obtain the corresponding run length code word, the described run length code word is made up of the group prefix and the group suffix corresponding to each other; the described group prefix is ​​a 0 run or 1 run determined by th...

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Abstract

The invention provides a chip testing data transmission method based on dual-run-length alternative coding. The chip testing data transmission method is based on FDR (False Discovery Rate) codes, and is a variable-to-variable-length compression method. Except for a large amount of run lengths 0, a test centralizes a large amount of run lengths 1, so that a method of alternative coding of 0/1 run lengths is provided, the later type of the run lengths can be converted by the former type of the run lengths, so that code words do not need to represent the type of the run lengths, and the length of the code words required by the type of the run lengths is reduced, thus the compression ratio is effectively improved. Meanwhile, a decoding circuit in the method is simple and is independent of a measured circuit, and based on that, the method has an excellent application prospect.

Description

technical field [0001] The invention relates to an integrated circuit testing method, in particular to a system chip testing data processing method. Background technique [0002] With the improvement of the technology level, the number of transistors integrated on the system chip SOC (System-on-a-chip) increases sharply. At the same time, in order to speed up the SoC design process, the design technology of IP (Intellectual Property) core multiplexing is usually widely used. In order to ensure that the product is free from defects, it is necessary to test the chip. At present, SoC testing is facing more and more difficulties, and the large amount of test data is one of the current difficulties. In order to cope with the pressure of the rapid growth of test data, it is generally effective to use compression technology to compress the test data. The test data compression technique first converts the test set T D Encode according to a certain encoding method, and the encoded...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M7/30
Inventor 程一飞詹文法吴琼朱世娟吴海峰何姗姗暴阳黄丽
Owner SHANGHAI TAIYU INFORMATION TECH
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