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Readout circuit and non-volatile memory using same

A read-out circuit, non-volatile technology, applied in read-only memory, static memory, digital memory information and other directions, can solve the problems of increased mismatch of two transistors, stop of read-out circuit function, increase of read-out circuit malfunction, etc.

Active Publication Date: 2014-04-23
PANASONIC SEMICON SOLUTIONS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, the gain of the amplifier decreases, and the mismatch between the pair transistors also increases, so the readout speed and accuracy decrease.
If the voltage is further reduced, the malfunction of the readout circuit will increase, and in the worst case, the function of the readout circuit may stop

Method used

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  • Readout circuit and non-volatile memory using same
  • Readout circuit and non-volatile memory using same
  • Readout circuit and non-volatile memory using same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0112] First, the readout circuit according to Embodiment 1 will be described.

[0113] figure 1 It is a block diagram of a nonvolatile memory including a readout circuit as an embodiment of the present invention. The first input 2 and the second input 3 of the readout circuit 1 are connected to the nonvolatile memory array 1000 through a column gate 1005 . The first input 2 and the second input 3 are respectively connected to a nonvolatile memory cell (sometimes simply referred to as a memory cell) or a reference cell included in the nonvolatile memory array 1000 .

[0114] It is assumed that the reference cell uses a nonvolatile memory cell similarly to the memory cell, or replaces the variable resistance element of the memory cell with a polysilicon resistor, a transistor, or the like. In addition, the reference cell is not limited to these configurations as long as it serves as a reference for comparison of the memory cells. The readout circuit 1 outputs a differential ...

Embodiment 2

[0132] Next, the readout circuit according to the second embodiment will be described using a transistor-level equivalent circuit.

[0133] figure 2 It is a circuit diagram of the readout circuit according to the second embodiment, and specifically shows the configuration of the first embodiment using transistors.

[0134] The readout circuit 20 consists of a current mirror pair 28 with a pair of P-channel transistors 28a, 28b, a first equalization transistor 29, a first discharge transistor pair 30 with a pair of N-channel transistors 30a, 30b, and a pair of P-channel transistors. A differential transistor pair 31 of channel transistors 31a and 31b and a second discharge transistor pair 32 having a pair of N channel transistors 32a and 32b are constituted.

[0135] The mirror current input drain 33 of the current mirror pair 28 is connected to the reference side input 22 (REF), and the mirror current output drain 34 is connected to the memory cell side input 21 (DAT). The ...

Embodiment 3

[0148] Next, as a third embodiment, a readout circuit in which a clamp transistor pair is added to the configuration of the second embodiment will be described. Figure 4 It is a circuit diagram of the readout circuit according to the third embodiment, and is an equivalent circuit diagram of the readout circuit shown in the first embodiment.

[0149] Readout circuit 300 includes clamp transistor pair 36 having a pair of N-channel transistors 36a, 36b. A clamp transistor pair 36 is inserted into the reference side input 22, the memory cell side input 21, respectively. Specifically, the mirror current input drain 33 is connected to the reference side input 22 via the drain and source of the N-channel transistor 36a. The mirror current output drain 34 is connected to the memory cell side input 21 via the drain and source of the N-channel transistor 36b. The respective gates of the N-channel transistors 36a, 36b are commonly connected to the clamp voltage input 35 . The clamp t...

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PUM

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Abstract

A readout circuit (1) is provided with the following: an electrical current load circuit (4) for supplying a load current from a power source to first and second inputs (2, 3); a first discharge circuit (6) for discharging the electric potential of the first and second inputs (2, 3) to ground level; an equalizing circuit (8) that equalizes the electric potential of the first and second inputs (2, 3); a differential circuit (11) for receiving the first and second inputs (2, 3) as differential inputs, and for outputting first and second readout outputs (9, 10), which are differential outputs; and a second discharge circuit (13) for discharging the electric potential of the first and second readout outputs (9, 10) to ground level.

Description

technical field [0001] The present invention relates to a nonvolatile memory using a variable resistance element and a readout circuit thereof, and particularly relates to a technique for realizing low-voltage operation and low power consumption. Background technique [0002] Conventionally, NAND flash memory or NOR flash memory using floating gate type or MONOS type transistors has been widely used as nonvolatile memory. In recent years, as a next-generation nonvolatile memory, variable resistance nonvolatile memories such as STT_MRAM (Spin Transfer Torque Magnetoresistive Random Access Memory), ReRAM (Resistance RAM), or PRAM (Phase Change RAM) have attracted attention. [0003] Data rewriting in the resistance variable memory is performed by passing a rewriting current through the resistance variable element and changing the resistance state thereof. The high resistance state is called HRS and the low resistance state is called LRS. The structure in which the current fl...

Claims

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Application Information

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IPC IPC(8): G11C13/00G11C11/15
CPCG11C2013/0042G11C13/0007G11C13/0004G11C16/28G11C7/062G11C13/0061G11C7/14G11C2013/0054G11C13/004G11C7/12G11C11/1673G11C11/1693
Inventor 富田泰弘
Owner PANASONIC SEMICON SOLUTIONS CO LTD
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