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Method for acquiring damaged bit line address in nonvolatile storage apparatus

A non-volatile storage, bit line technology, applied in static memory, instruments, etc., can solve problems such as time-consuming

Active Publication Date: 2014-05-07
EON SILICON SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, traditionally, after the verification procedure, an additional calculation procedure is usually required to set the address of the defective memory cell for subsequent setting of the redundant storage cell. This additional calculation procedure is time consuming disadvantage

Method used

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  • Method for acquiring damaged bit line address in nonvolatile storage apparatus
  • Method for acquiring damaged bit line address in nonvolatile storage apparatus
  • Method for acquiring damaged bit line address in nonvolatile storage apparatus

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Embodiment Construction

[0032] In order to fully understand the purpose, characteristics and effects of the present invention, the present invention will be described in detail through the following specific embodiments, and in conjunction with the attached drawings, as follows:

[0033] See first figure 1 , is a flowchart of a method for reading a damaged bit line in an embodiment of the present invention. The obtaining method includes the following steps: S100, reset the page buffer circuit; S200, perform a bit line damage test to record the state data of whether the bit line is damaged in the page buffer circuit; S300, according to the bit line of each memory cell The address sequence, read the state data of whether each bit line in the page buffer circuit is damaged in sequence; The address is the address data of the damaged bit line.

[0034] see next figure 2 , is a partial circuit block diagram for obtaining the address of a damaged bit line in an embodiment of the present invention. The ...

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Abstract

The invention discloses a method for acquiring damaged bit line address in a nonvolatile storage apparatus. The nonvolatile storage apparatus includes a storage cell array and many word lines across the storage cell array, wherein, each of bit lines comprises a first end and a second end, and many bit lines are divided into a first group and a second group. A detecting method comprises the following steps: applying a power supply voltage (charging) or a grounding voltage (discharging) to bit lines of a specific group; detecting the bit lines by two detection stages (open circuit and short circuit detection) by using the characteristics that the damaged bit line can not be normally charged or discharged; furthermore, acquiring address data of the damaged bit line by sequential reading of damage state data of each bit line recorded in a page buffer circuit without using extra calculation programs for estimation of address of the damaged bit line.

Description

technical field [0001] The present invention relates to a memory address reading method, in particular to a method for reading the address of a damaged bit line in a non-volatile memory device. Background technique [0002] In a non-volatile memory device, due to defects in semiconductor manufacturing process technology, the bit line may be broken or short-circuited with an adjacent bit line. For example, as the size of the non-volatile memory device shrinks, adjacent bit lines will be quite close to each other, and therefore it is very easy to cause an improper short circuit phenomenon caused by the contact window of the bit line being too close to the adjacent bit line during the manufacturing process. [0003] Therefore, in non-volatile memory devices, verification operations are necessary to confirm that charges are properly injected into memory cells by programming operations. Non-volatile memory devices are typically tested by verifying operating procedures to determi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12
Inventor 赤荻隆男陈敦仁
Owner EON SILICON SOLUTION