A stt-mram cache design method
A design method and cache technology, applied in computing, energy-saving computing, information storage, etc., can solve problems such as difficult universal and effective solutions, increase the static power consumption of the chip, and different memory access behaviors, and improve the performance of the chip. rate, reduce write power consumption, and improve performance
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[0028] The working principle of the STT-MRAM storage unit involved in the present invention is as follows figure 1 shown. STT-MRAM memory cells generally adopt 1T1J (1Transistor and 1MTJ). Transistors control access to MTJ data. The structure of MTJ is divided into free layer, reference layer and intermediate oxide layer. Wherein the magnetization direction of the reference layer is fixed. By applying currents in different directions to the MTJ, the magnetization direction of the free layer can be changed. If the magnetization direction of the free layer is the same as that of the reference layer, the resistance value of the MTJ becomes smaller, and it can be regarded as storing logic "0". Otherwise, a logic "1" is stored. When reading the data of the memory cell, the word line is set to be valid, and a small voltage of 0.1V is applied between the bit line BL and the source line SL. According to the similarities and differences of the magnetization directions of the free ...
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