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FFT (fast fourier transform)/IFFT (inverse fast fourier transform) method and device for prime length

A prime number and data technology, applied in complex mathematical operations and other directions, can solve the problem of consuming chip area, and achieve the effect of avoiding complex multiplication, reducing the number of gate circuits, and achieving high speed.

Inactive Publication Date: 2014-05-21
WUXI HANXING ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 3. The traditional multiplication-based FFT / IFFT algorithm consumes chip area;
[0007] 4. Practical applications require that FFT / IFFT can be implemented on different FPGAs, so the FFT / IFFT processor architecture must have high portability

Method used

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  • FFT (fast fourier transform)/IFFT (inverse fast fourier transform) method and device for prime length
  • FFT (fast fourier transform)/IFFT (inverse fast fourier transform) method and device for prime length
  • FFT (fast fourier transform)/IFFT (inverse fast fourier transform) method and device for prime length

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1，5FFT example pic specific Embodiment approach

[0034] Such as Figure 1-4 as shown,

[0035] The calculation formula of 5-POINT FFT is: F5=PL*G5*H5*PR

[0036] Where PL and PR are output and input permutation matrices

[0037] PL = 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 ...

Embodiment 2，13FFT example pic specific Embodiment approach

[0051] Such as figure 1 , 5 -7,

[0052] The calculation formula of 13-POINT FFT is: F13=PL*G13*H13*PR

[0053] Where PL and PR are output and input permutation matrices

[0054] PR = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ...

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Abstract

The invention provides an FFT (fast fourier transform) / IFFT (inverse fast fourier transform) method and an FFT / IFFT device for a prime length. The device comprises an input replacement module, a real coefficient cyclic convolution module, a complex coefficient cyclic convolution module and an output replacement module. By the use of a systolic array structure, the device disclosed by the invention is high in speed; by the use of a real coefficient cyclic convolution structure, the complex multiplication is avoided, and multiplication is realized through an adder network; the number of gate circuits can be effectively reduced; the architecture is suitable for realization of different types of FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits) from different factories.

Description

technical field [0001] The present invention relates to digital multimedia, in particular to FFT (Fast Fourier Transform, Fast Fourier Transform) / IFFT (Inverse Fast-Fourier-Transform, Inverse Fast Fourier Transform) processing of prime number point lengths for digital multimedia and communication systems The device architecture belongs to the field of digital signal processing. Background technique [0002] In the development of digital signal processing, many algorithms such as correlation, filtering, convolution, etc. can be transformed into DFT (Discrete Fourier Transform, discrete Fourier transform) to achieve. However, the calculation amount of direct calculation of DFT is proportional to the square of the length N of the transformation interval. Decomposing the N-point DFT into several shorter DFTs can greatly reduce the number of multiplications, and then there is a fast Fourier transform. FFT is a fast algorithm of DFT. Its proposal greatly reduces the amount of cal...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 周园
Owner WUXI HANXING ELECTRONICS