Anti-single event upset and anti-single event transient resettable scanning structure D trigger

A single-event transient and anti-single-event technology, which is applied in the direction of pulse generation, electrical components, and electric pulse generation, can solve the problems of anti-single-event flipping ability and anti-single-event transient.

Active Publication Date: 2014-05-28
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0010] The technical problem to be solved by the present invention is to propose an anti-single event...

Method used

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  • Anti-single event upset and anti-single event transient resettable scanning structure D trigger
  • Anti-single event upset and anti-single event transient resettable scanning structure D trigger
  • Anti-single event upset and anti-single event transient resettable scanning structure D trigger

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Embodiment Construction

[0039] figure 2 It is a schematic diagram of the logic structure of the anti-single event reversal and single event transient scanning structure D flip-flop of the present invention. The present invention consists of a clock circuit (such as image 3 shown), snubber circuits such as Figure 4 shown), scan control buffer circuit (such as Figure 5 shown), reset snubber circuit (as Figure 6 shown), the master latch (as Figure 7 shown), slave latches (as Figure 8 shown), the output buffer circuit (such as Figure 9 shown) composition. The anti-single-event reversal and anti-single-event transient resettable D flip-flop of the present invention has five input terminals and one output terminal. The five input terminals are clock signal input terminal CK, data signal input terminal D, scanning control signal input terminal SE, scanning data input terminal SI and reset signal input terminal RN; the output terminal is Q. The clock circuit receives CK, and outputs c1, c2 an...

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Abstract

The invention discloses an anti-single event upset and anti-single event transient resettable scanning structure D trigger, for the purpose of solving the problems of not high anti-single event upset capability and not high anti-single event transient capability of a conventional resettable scanning structure D trigger. The resettable scanning structure D trigger provided by the invention is composed of a buffer circuit, a scanning control buffer circuit, a reset buffer circuit, a clock circuit, a master latch register, a slave latch register and an output buffer circuit. The master latch register and the slave latch register are latch registers with redundancy reinforcement. The master latch register and the slave latch register are connected in series and are both connected with the clock circuit and the reset buffer circuit. The master latch register is also connected with the buffer circuit and the scanning control buffer circuit. The slave latch register is also connected with the output buffer circuit. According to the invention, mutually redundant C<2>MOS circuits are separated from the master latch register and the slave latch register so that the anti-single event upset capability is improved. The buffer circuit enables no errors to be generated under a single event transient pulse which lasts for quite a long time. A dual-mode redundancy pathway further enhances the anti-single event upset capability.

Description

technical field [0001] The present invention relates to a master-slave D flip-flop with a reset structure and a scan structure, in particular to a resettable scan against single event upset (Single Event Upset, SEU) and single event transient (Single Event Transient, SET). Structural D flip flops. Background technique [0002] There are a large number of high-energy particles (protons, electrons, heavy ions, etc.) in the universe. After the sequential circuit in the integrated circuit is bombarded by these high-energy particles, the state it maintains may be reversed. This effect is called the single event reversal effect. The higher the LET (Linear Energy Transfer) value of the bombardment IC, the easier it is to produce single event upset effects. After the combined circuit in the integrated circuit is bombarded by these high-energy particles, it is possible to generate a transient electric pulse. This effect is called the single event transient effect. The higher the LET...

Claims

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Application Information

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IPC IPC(8): H03K3/012
Inventor 陈建军杨茂森沈广振陈书明孙永节郭阳梁斌池雅庆胡春媚刘祥远
Owner NAT UNIV OF DEFENSE TECH
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