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Optimization of stress influence model in integrated circuit SPICE model

A technology that affects models and integrated circuits. It is used in electrical digital data processing, special data processing applications, instruments, etc. It can solve problems such as the inability to accurately describe the effect of stress on transistors, and achieve the effect of helping design and manufacturing.

Active Publication Date: 2014-06-04
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the existing stress effect model cannot accurately describe the effect of stress on transistor performance, therefore, there is a need for an improved stress effect model in the SPICE model

Method used

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  • Optimization of stress influence model in integrated circuit SPICE model
  • Optimization of stress influence model in integrated circuit SPICE model
  • Optimization of stress influence model in integrated circuit SPICE model

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Embodiment Construction

[0037] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0038] At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0039] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way taken as limiting the invention, its application or uses.

[0040] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the descript...

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Abstract

The invention relates to a method and device for optimizing a stress influence model in an integrated circuit SPICE model and a method for manufacturing an integrated circuit. The influence of stress on transistor parameters is calculated by the stress influence model through layout parameters and process model parameters relevant to a process. The method for optimizing the stress influence model comprises the steps that the value of at least one layout parameter of a plurality of layout areas in a layout and the value of at least one process parameter of multiple corresponding wafer areas on a wafer are obtained; a function for expressing the dependency of the process parameters on the layout parameters is built according to the obtained values of the layout parameters and the values of the process parameters; the function is used as the process model parameters to be applied to the stress influence model. The stress influence model obtained through the method can reflect the influence of process parameter fluctuation on transistor performance, therefore, the characteristics of a transistor or other devices can be simulated more accurately, and design and manufacturing of the integrated circuit are facilitated.

Description

technical field [0001] The present disclosure relates generally to the design and manufacture of integrated circuits (ICs), and more particularly to the optimization of stress effect models in SPICE models of integrated circuits. Background technique [0002] With the development of integrated circuit technology, stress as a factor affecting the performance of transistor devices has been widely studied and applied. Stress on transistors comes from many sources, including shallow trench isolation (STI), source / drain embedded SiGe (eSiGe), silicide, replacement gates, and more. These stresses have a significant impact on carrier mobility, threshold voltage, and other parameters such as drain-induced barrier lowering (DIBL), carrier saturation velocity, etc. Therefore, when designing integrated circuits, the influence of stress needs to be considered. [0003] On the other hand, the modeling and simulation of integrated circuits has become an indispensable means in the proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F17/5081G06F30/398G06F30/367
Inventor 殷华湘
Owner SEMICON MFG INT (SHANGHAI) CORP