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Matrix multiplication calculating device and matrix multiplication calculating method both oriented to programmable algebra processor

A matrix multiplication and computing device technology, applied in the field of matrix multiplication computing devices, can solve the problem of low execution efficiency of large-scale and small matrix multiplication, and achieve the effect of improving computing efficiency

Active Publication Date: 2014-07-02
上海思朗科技有限公司
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Problems solved by technology

[0018] The technical problem to be solved by the present invention is the problem that the existing matrix multiplication method and device have low execution efficiency for the multiplication of large-scale small matrices

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  • Matrix multiplication calculating device and matrix multiplication calculating method both oriented to programmable algebra processor
  • Matrix multiplication calculating device and matrix multiplication calculating method both oriented to programmable algebra processor
  • Matrix multiplication calculating device and matrix multiplication calculating method both oriented to programmable algebra processor

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Embodiment Construction

[0027] Aiming at the existing situation, the present invention proposes a method and device for efficiently calculating matrix multiplication, which is especially suitable for large-scale small matrix multiplication.

[0028] The large-scale small matrix multiplication vectorization device proposed by the present invention includes: a multi-granularity parallel memory 10 , a data buffer device 20 , a data broadcast buffer device 30 , and a vector operation device 40 . in:

[0029] The multi-granularity parallel memory 10 is used to store a plurality of matrices to be multiplied, broadcast indexes and matrix multiplication results. The broadcast index is used to perform a broadcast operation on each data in the matrix. The read / write bit width of the memory is consistent with the bit width of the register file 201 of the data cache device, the bit width of the relevant registers in the data broadcast buffer device, and the operation size of the vector operation device 40, deno...

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Abstract

The invention discloses a matrix multiplication calculating device and a matrix multiplication calculating method. The matrix multiplication calculating device comprises a multi-granularity parallel storer, a data caching device, a data broadcast caching device and a vector operation device. Parallel optimized processing is performed on matrix multiplication which is small in matrix size and large in operation quantity in actual application by adopting a programmably-configured DSP (digital signal processor) chip and combing a high-efficiency vectorized matrix multiplication scheme, and the matrix multiplication calculating device and the matrix multiplication calculating method have the advantages of being high in operation speed, high in parallel granularity and small in access number.

Description

technical field [0001] The present invention relates to the technical field of data processing, and more specifically, to a matrix multiplication computing device and method based on a programmable algebraic processor. Background technique [0002] Matrix multiplication is a basic operation in scientific computing, which is widely used in complex computing fields such as signal processing, image processing, radar, sonar, communication, etc., and because its computational complexity is O(n 3 ), making matrix multiplication often become the most time-consuming operation in the calculation process of the algorithm, which in turn affects the performance of the entire algorithm. Matrix multiplication operations are divided into large matrix multiplication and small matrix multiplication. Large matrix multiplication has an exponential increase in the amount of operations due to its huge row and column values. In recent years, it has received widespread attention. A general process...

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Application Information

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IPC IPC(8): G06F17/16
Inventor 郭晓龙王晓琴王伟康吴军宁林啸郭璟张森赵旭莹
Owner 上海思朗科技有限公司
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