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Wafer-level CSP structure with insulated side wall and packaging method thereof

A technology of packaging structure and sidewall insulation, applied in electrical components, electrical solid devices, circuits, etc., can solve the problems of uneven heating temperature during reflow, unbalanced electrodes at both ends, chip leakage, etc., to eliminate the phenomenon of tin creep, overcome Leakage problem, the effect of reducing production cost

Inactive Publication Date: 2014-07-02
JIANGYIN CHANGDIAN ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002]In the existing wafer-level CSP (Chip Scale Package) packaging structure, the silicon around the chip is exposed in the assembly environment. During the placement and reflow process, the solder balls Or the electrode area is likely to cause part of the solder to climb to the exposed silicon on the side wall of the chip due to excessive printing of solder paste, resulting in chip leakage
At the same time, for extremely small package products, such as 0402, 0210, 01005 and other package products, such as Figure 1 as shown in the left picture, its own weight is very light, if there is a difference in the amount of solder paste printed on the two electrodes during the surface mount process, and the reflow heating temperature is uneven, resulting in If the two ends of the electrodes are unbalanced, it is very easy to cause one end of the device to lift up, forming a "tombstone" phenomenon, such as Figure 1 is shown on the right, resulting in poor placement of the device

Method used

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  • Wafer-level CSP structure with insulated side wall and packaging method thereof
  • Wafer-level CSP structure with insulated side wall and packaging method thereof
  • Wafer-level CSP structure with insulated side wall and packaging method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0044] see figure 2 , a wafer-level CSP packaging method with sidewall insulation of the present invention, its technological process is as follows:

[0045] Executing step 1: providing a wafer with a chip electrode array;

[0046] Execute step 2: open a wide groove that does not cut through the wafer along the scribing lane of the wafer on the surface of the wafer;

[0047] Execute step 3: deposit an insulating layer on the surface of the wafer and the inner wall of the wide groove, and solidify and shape;

[0048] Executing step 4: opening an insulating layer opening through the insulating layer above the chip electrode;

[0049] Executing Step 5: Electroless plating of metal bumps in the opening of the insulating layer;

[0050] Execute Step 6: Cover the metal bumps with film layer I and turn over the mold so that the back of the wafer faces upwards;

[0051] Execute step 7: Thinning the back of the wafer until the bottom of the wide groove is exposed;

[0052] Execut...

Embodiment 2

[0068] see figure 2 , a wafer-level CSP packaging method with sidewall insulation of the present invention, its technological process is as follows:

[0069] Executing step 1: providing a wafer with a chip electrode array;

[0070] Execute step 2: open a wide groove that does not cut through the wafer along the scribing lane of the wafer on the surface of the wafer;

[0071] Execute step 3: deposit an insulating layer on the surface of the wafer and the inner wall of the wide groove, and solidify and shape;

[0072] Executing step 4: opening an insulating layer opening through the insulating layer above the chip electrode;

[0073] Executing Step 5: Electroless plating of metal bumps in the opening of the insulating layer;

[0074] Execute Step 6: Flip-chip to film layer Ⅰ, so that the back of the wafer faces up;

[0075] Execute step 7: Thinning the back side of the wafer;

[0076] Executing step 8: coating layer II on the back of the above-mentioned wafer and turning ...

Embodiment 3

[0086] Embodiment three, see Figure 28 and Figure 29

[0087] The difference between this embodiment and Embodiment 1 and Embodiment 2 is that: the surface of the silicon substrate 101 on the other side of the chip electrode 110 is provided with a back protection layer 130 to enhance the strength of the wafer-level CSP packaging structure.

[0088] The back protection layer is formed on the other side of the wafer 100 by film sticking or printing before coating the film layer II 520 on the surface of the wafer 100 , and is divided by a dicing knife or laser when forming the dividing lines.

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Abstract

The invention discloses a wafer-level CSP structure with an insulated side wall and a packaging method of the wafer-level CSP structure with the insulated side wall and belongs to the technical field of semiconductor package. The wafer-level CSP structure with the insulated side wall comprises a silica-based body (101) with a plurality of chip electrodes (110), and insulating layers (200), wherein the insulating layers (200) are arranged on the surface of the side, provided with the chip electrodes (110), of the silica-based body (101) and the side wall of the silica-based body (101), insulating layer openings (201) are formed in the insulating layers (200) and are located over the chip electrodes (110), and metal protrusions (400) are arranged in the insulating layer openings (201) and fixedly connected with the chip electrodes (110). According to the wafer-level CSP structure with the insulated side wall, the wicking effect of the side wall is effectively eliminated, electric leakage of chip scale package is avoided, the yield of devices is increased, the packaging method is easy, and manufacturing cost is reduced.

Description

technical field [0001] The invention relates to a wafer-level CSP packaging structure and a packaging method thereof, in particular to a wafer-level CSP packaging structure with insulating side walls and a packaging method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] In the existing wafer-level CSP (Chip Scale Package) packaging structure, the silicon around the chip is exposed in the assembly environment. During the placement and reflow process, the solder balls or electrode areas are prone to partial soldering due to excessive printing of solder paste. Climb to the exposed silicon on the side wall of the chip, causing chip leakage. At the same time, for extremely small package products, such as 0402, 0210, 01005 and other package products, such as figure 1 As shown in the left picture, its own weight is very light. If there is a difference in the amount of solder paste printed on the two electrodes during the surface ...

Claims

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Application Information

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IPC IPC(8): H01L23/31H01L21/50
CPCH01L2224/11
Inventor 张黎陈锦辉赖志明孙超
Owner JIANGYIN CHANGDIAN ADVANCED PACKAGING
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