Low-cost wafer-level CSP method and structure

Abstract

The invention discloses a low-cost wafer-level CSP method and structure, and belongs to the technical field of semi-conductor packaging. The method comprises the steps that a wafer with a chip electrode array is provided; a metal protruding point is formed on the surface of the chip electrode array; a wide groove is formed along a scribing channel of the wafer, extends into the wafer, and does not penetrate through the wafer; an insulation layer is printed on the wafer, solidified and formed; the insulation layer and the metal protruding point are cut to form a metal protruding point tangent plane; a metal protecting layer is formed on the surface of the metal protruding point tangent plane; the wafer is segmented along the scribing channel of the wafer again, a segmenting channel narrower than the wide groove is formed, and then the single low-cost wafer-level CSP structure is formed through segmenting. According to the wafer-level CSP structure, the side wall is provided with the insulation layer, the tin climbing phenomenon of the side wall is effectively eliminated, the electric leakage problem of chip size package is resolved, the yield of devices is increased, and the low-cost wafer-level CSP method is simple, and reduces production cost.

Description

technical field [0001] The invention relates to a wafer-level CSP packaging method and its packaging structure, in particular to a low-cost wafer-level CSP packaging method and its packaging structure, belonging to the technical field of semiconductor packaging. Background technique [0002] In the existing wafer-level CSP (Chip Scale Package) packaging structure, the silicon around the chip is exposed in the assembly environment. During the placement and reflow process, the solder balls or electrode areas are prone to partial soldering due to excessive printing of solder paste. Climb to the exposed silicon on the side wall of the chip, causing chip leakage. At the same time, for extremely small package products, such as 0402, 0210, 01005 and other package products, such as figure 1 As shown in the left picture, its own weight is very light. If there is a difference in the amount of solder paste printed on the two electrodes during the surface mount process, and the reflow ...

AI Technical Summary

Problems solved by technology

[0002]In the existing wafer-level CSP (Chip Scale Package) packaging structure, the silicon around the chip is exposed in the assembly environment. During the placement and reflow process, the solder balls Or the electrode area is likely to cause part of the solder to climb to the exposed silicon on the side wall of the chip due to excessive printing of solder paste, resulting in chip leakage

At the same time, for extremely small packaged products, such as 0402, 0210, 01005 and other packaged products, such as Figure 1 as shown in the left picture, its own weight is very light, if there is a difference in the amount of solder paste printed on the two electrodes during the surface mount process, and the reflow heating temperature is uneven, resulting in Unbalanced electrodes at both ends can easily cause one end of the device to lift up, forming a "tombstone" phenomenon, such as Figure 1 is shown on the right, resulting in poor placement of the device

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