An interface circuit capable of tolerating high voltage input

Abstract

An interface circuit capable of tolerating high voltage input, I / O pin connecting external, a pull-up / pull-down structure provides high / low power level of output to the I / O pin. An impedance control circuit shuts the pull-up / pull-down structure in receiving mode, and activates the pull-up / pull-down structure in transmission mode. A pull-up / pull-down protection structure protects the pull-up / pull-down structure in receiving mode. A gate protection circuit provides protection voltage to the pull-up protection structure in receiving mode. A N-well bias circuit provides a bias voltage that equaling to internal power supply for the pull-up structure and the N-well where the PMOS located in of the pull-up protection structure in transmission mode; and in a receiving mode, if voltage of the I / O pin is higher than voltage of the internal power supply, providing a bias voltage that approaching to voltage of the I / O pin to the pull-up structure and the N-well where the PMOS located in of the pull-up protection structure, otherwise, providing a bias voltage that equaling to internal power supply. Well bias drive circuit provides driving signal to the N-well bias circuit in transmission mode.

Description

technical field [0001] The invention relates to an interface circuit capable of withstanding external high voltage input. Background technique [0002] With the continuous improvement of CMOS technology, the circuit design is rapidly evolving to deep submicron technology, and the power supply voltage is gradually reduced to 2.5V or 1.8V. However, some peripheral device chips still work at a higher voltage level, such as 3.3V or 5V, resulting in a system that may have different voltage standards running at the same time. For example, when a chip with an internal interface circuit operating voltage of 2.5V must be connected to a 3.3V or 5V external interface, or a chip with an internal interface circuit operating voltage of 3.3V must be connected to a 5V external interface, if If the withstand voltage problem is not considered in the chip I / O interface design, various problems will be caused, such as oxide layer breakdown, hot carrier degradation effect and leakage current, e...

AI Technical Summary

Problems solved by technology

Existing NMOS-blocking technology, such as the dynamic gate bias mentioned in "A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes" published by M.-D.Ker on circuits and systems in 2004 Circuits and charge pump circuits, etc., although high withstand voltage design can be realized, a large number of auxiliary circuits are needed to achieve protection purposes, the circuit control is complicated, and it will occupy a large amount of chip area

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