FPGA zero-dynamic power consumption design method

A design method and dynamic power consumption technology, applied in the direction of data processing power supply, etc., can solve problems such as invalid power consumption, and achieve the effect of reducing power consumption

Active Publication Date: 2014-07-16
SHANGHAI SPACEFLIGHT ELECTRONICS & COMM EQUIP RES INST
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  • FPGA zero-dynamic power consumption design method
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  • FPGA zero-dynamic power consumption design method

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[0031] The following will clearly and completely describe and discuss the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the present invention. Obviously, what is described here is only a part of the examples of the present invention, not all examples. The embodiments, all other embodiments obtained by those of ordinary skill in the art without creative work, fall within the protection scope of the present invention.

[0032] In order to facilitate the understanding of the embodiments of the present invention, specific embodiments will be used as an example for further explanation and description with reference to the accompanying drawings, and each embodiment does not constitute a limitation to the embodiments of the present invention.

[0033] The invention provides a FPGA zero dynamic power design method, which achieves the effect of zero dynamic power consumption by turning off the working clock of the sequential ...

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Abstract

The invention discloses an FPGA zero-dynamic power consumption design method. A system clock tree and local clock trees are established. Clock management logic is established according to a state machine method and is established through the steps that functional logic or clock signal work of a clock drive source is identified as a work state, the function logic or the stagnation of the clock drive source is identified as a stop state, a hanging state used for judging the control method of a clock is established, and information interaction used for switching working modes and multiple systems or multiple clock domains is established. By setting the clock management logic based on state detection and clock drive control, the clock drive source for the corresponding functional logic is powered off, and the power consumption lowering design method for the 0Hz clock is achieved. Thus, the duty ratio of reactive power in the device is controlled, and the maximum efficiency for use of dynamic power consumption resources is achieved.

Description

technical field [0001] The invention relates to the technical field of power consumption design of electronic products, in particular to an FPGA zero dynamic power consumption design method. Background technique [0002] In the design technology of contemporary electronic products, with the increase of the amount of information data, the processing speed of electronic products is also increasing day by day. Affected by system design margins, expansion and other performance and design requirements, embedded electronic systems generally have a contradiction between excess processing performance and limited processing task requirements, which will cause a large number of space and time invalid operations in the system, resulting in overall energy consumption. invalid consumption on . If during system operation, all invalid operations in time and space have no power consumption, then the system is under ideal power consumption operation conditions, that is, the so-called zero-p...

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Application Information

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IPC IPC(8): G06F1/32
Inventor 陈晓强
Owner SHANGHAI SPACEFLIGHT ELECTRONICS & COMM EQUIP RES INST
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