Semiconductor element and manufacturing method thereof

A manufacturing method, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc.
CN103972285AActive Publication Date: 2014-08-06UNITED MICROELECTRONICS CORP
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
UNITED MICROELECTRONICS CORP
Publication Date
2014-08-06

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Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a semiconductor substrate, a grid structure, at least one epitaxial layer, an interlayer dielectric layer, at least one contact hole, at least one metal silicide and a fluorine-containing layer. The semiconductor substrate is provided with at least one grid region and at least one source / drain region adjacent to the grid region. The grid structure is arranged in the grid region on the semiconductor substrate. The epitaxial layer is arranged in the source / drain region of the semiconductor substrate. The semiconductor substrate, the grid structure and the epitaxial layer are covered with the interlayer dielectric layer. The contact hole penetrates through the interlayer dielectric layer until the epitaxial layer is exposed outside . The metal silicide is located on the part, at the bottom of the contact hole, of the epitaxial layer. The fluorine-containing layer is arranged in or on the epitaxial layer and arranged on the periphery of a metal silicide layer.
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Description

technical field

[0001] The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a semiconductor element with a fluorine-containing layer in the source / drain region and a manufacturing method thereof. Background technique

[0002] As the integration level of integrated circuits (ICs) becomes higher and higher, the line width and geometric dimensions of semiconductor elements also step into sub-micron physical dimensions. Limited by the nature of the material, the increase in the degree of integration increases the junction resistance between the semiconductor layer and the external contact metal. Therefore, there is still a need to develop a semiconductor device with lower junction resistance to meet the needs of the industry.

[0003] In the fabrication of the existing plug structure, a self-aligned silicon metallization process (self-aligned silicide, salicide) is generally used to form a metal silicide at the junction between t...

Claims

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