Side wall structure, preparation method of side wall structure, cmos device

Abstract

The invention provides a side wall structure, a manufacturing method of the side wall structure and a CMOS device with the side wall structure. An existing second side wall structure is changed, an original second side wall of an ON structure is changed to a second side wall of an ONO structure, and therefore the thickness of the nitriding layer in the second side wall is reduced; meanwhile, an oxidation layer is deposited on the nitriding layer to ensure that an original source / leak ion implantation region is not changed, and accordingly a stacked ONO structure is formed; after technology for heating processing is carried out, due to the fact that stress of the thinned nitriding layer on an active region is obviously reduced, dislocation defects caused by the nitriding layer to the active region are reduced, the phenomenon of electric leakage of elements is reduced, and the yield of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a side wall structure for reducing the leakage effect of VDD, a preparation method thereof, and a CMOS device including the side wall structure. Background technique [0002] After the semiconductor manufacturing process enters the nanoscale, the sidewall structure is generally used in CMOS devices. The sidewall structure surrounds the gate, which can protect the polysilicon gate, define the source-drain ion implantation area, prevent self-aligned silicide from bridging, and To prevent the source / drain punchthrough problem caused by high-intensity and large-dose source / drain implantation too close to the channel. [0003] The existing side wall structure usually includes a first side wall and a second side wall, and the first side wall and the second side wall are made of insulating dielectric materials; wherein, the first side wall can be made of silicon oxide, silicon ni...

AI Technical Summary

Problems solved by technology

[0004] After the sidewall structure is formed, ion implantation is performed, and then thermal activation, followed by a series of furnace tube process, CVD process and other heat treatment processes, the temperature used in these heat treatment processes is relatively high, and the second sidewall of the ON structure Among them, the thickness of the nitride layer is relatively large. After the above-mentioned heat treatment process, that is, the high-temperature environment, it will generate a lot of stress on the subsequently formed active region, which is likely to cause lattice dislocation defects in the active region, thereby Increase the component leakage (VDD Leakage, here, VDD refers to the component pin of the drain), which seriously affects the quality of the chip

The reasons for this problem are as follows: due to the different thermal expansion coefficients of the nitride layer and the oxide layer, the inherent intrinsic stress and thermal expansion force of the nitride layer cannot be adjusted at the interface during the heat treatment process. The stress generated at the cross-section of the oxide layer and the oxide layer will cause dislocation defects in the active area, and even cause the wafer to warp or break in severe cases

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