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Isomerous CMP (Chip Multi-Processor) static state task scheduling method

A task scheduling and task technology, applied in the direction of program startup/switching, resource allocation, multi-program device, etc., can solve the problem of excessive processor core idle time, untimely processing of redundant tasks, and affecting heterogeneous CMP performance, etc. problem, to achieve the effect of improving resource utilization, reducing communication overhead, and improving task scheduling efficiency

Inactive Publication Date: 2014-08-13
HARBIN ENG UNIV
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AI Technical Summary

Problems solved by technology

However, the task scheduling algorithm in the existing heterogeneous CMP is still not ideal. There are problems such as too single task priority selection, too many idle time periods on the processor core, and untimely processing of redundant tasks, which seriously affects the performance of heterogeneous CMP.

Method used

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  • Isomerous CMP (Chip Multi-Processor) static state task scheduling method
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  • Isomerous CMP (Chip Multi-Processor) static state task scheduling method

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Embodiment Construction

[0045] The static task scheduling method of heterogeneous CMP of the present invention comprises the following steps:

[0046] Step 1: If figure 1 , figure 2 As shown, use the linear clustering method to merge all tasks that meet the task merging conditions in the DAG graph into their parent tasks;

[0047] Depth-first traverses all tasks in the DAG graph, and merges all tasks that meet the merging conditions. By merging tasks whose communication overhead accounts for a large proportion of the total task completion time, the total task completion time is shortened and the task graph is optimized.

[0048] Two conditions must be met at the same time for task merging:

[0049] (1) The current task has a unique parent task and is the only child task of the unique parent task;

[0050] (2) The communication overhead of the current task and its only parent task is greater than or equal to its maximum computing overhead on different processor cores, that is, C(v i ,v j )≥max{...

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Abstract

The invention relates to an isomerous CMP (Chip Multi-Processor) static state task scheduling method. The method is characterized in that 1, all tasks conforming to task merger conditions in a DAG (Directed Acyclic Graph) are incorporated into parent tasks by using a linear cluster method; 2, the DAG is layered according to a top-to-bottom method, and the smaller the layer value is, the higher the task priority is higher; a key task has the highest priority in the tasks of the same layer, and other non-key tasks are added into a dispatching list according to the descending order of task priority weight numbers; 3, a primary task is obtained from the dispatching list for distribution, the copied tasks in a task mapping graph are subjected to redundancy detection layer by layer, and redundancy tasks in the task mapping graph are deleted; the task mapping graph from which the redundancy tasks are deleted is adjusted, and the earliest execution completion time of each subsequent task is recalculated.

Description

technical field [0001] The invention relates to a static task scheduling method of heterogeneous CMP. Background technique [0002] With the deepening of the application of computer systems in people's lives, the design of computer systems has also entered a new era. In the past, the improvement of processor performance was often achieved by increasing its main frequency or increasing the degree of parallelism at the instruction level. However, as the chip manufacturing process is gradually approaching the technical limit, in terms of computer architecture, it is no longer possible to improve system performance by increasing the main frequency of the processor. The chip can no longer withstand the increase in heat dissipation caused by a large number of transistors, and the increase in the main frequency has also led to an increase in chip energy consumption. The superscalar technology that can improve instruction-level parallelism has also encountered a bottleneck, and it...

Claims

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Application Information

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IPC IPC(8): G06F9/48G06F9/50
Inventor 李静梅孙冬微韩启龙
Owner HARBIN ENG UNIV
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