Reset circuit low in power consumption and high in stability

Abstract

The invention discloses a reset circuit low in power consumption and high in stability. The reset circuit comprises a POR current generation circuit, a power-down detection module, a charging and discharging module and a Schmitt shaping module. The POR current generation circuit is used for generating POR currents in the power-on process for charging the charging and discharging module and providing voltage offsets for a discharging channel of the power-down detection module. The power-down detection module is connected with the POR current generation module, and opens the discharging channel when voltage drop is large for discharging the charging and discharging module so that reset output can be generated to make a follow-up circuit reset. The charging and discharging module is charged and discharged under the control of the POR currents and the discharging channel of the power-down detection module, so that original reset voltages are output according to requirements. The Schmitt shaping module is used for shaping the original reset voltages output by the charging and discharging module into regular digital reset signals with small rise and drop time delay. According to the reset circuit, the anticipated low power consumption is achieved, the functions of power-on reset and power-down detection and reset are successfully achieved, hysteresis voltages are well provided through a Schmitt trigger, and therefore stability of the whole circuit is guaranteed.

Description

technical field [0001] The invention relates to a reset circuit, in particular to a reset circuit with low power consumption and high stability, and belongs to the field of CMOS analog circuit design. Background technique [0002] The working principle and design and implementation of a typical power-on reset circuit are simple and feasible. figure 1 It is a high-level power-on reset circuit in the prior art. The upper end of the capacitor C is connected to the upper end of the power supply VDD and the lower end is connected to the upper end of the resistor R to output a reset signal RESET, and the lower end of the resistor R is grounded. RESET is the power supply VDD, and then VDD charges the capacitor C, and the charging current generates a voltage on the resistor R, forming a voltage difference between the lower end of the capacitor C and GND, and the output before the voltage is greater than the high level threshold of the subsequent circuit is subsequently The circuit ...

AI Technical Summary

Problems solved by technology

The power-on reset circuit with this structure has the following three disadvantages: first, the capacitance of the capacitor needs to be relatively large and occupies a large area;

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