Task scheduling method, based on virtual partitioning, for reconfigurable system

Abstract

The invention discloses a task scheduling method, based on virtual partitioning, for a reconfigurable system. According to the method, task significance parameters are defined according to the reappearance frequency of tasks, virtual partitioning is carried out on reconfigurable resources, and partitioning management is carried out on the tasks at different significance levels. When task significance values are increased, some tasks are transferred from one partition to another partition. When the tasks are completed, the configuration of the tasks is retained as far as possible instead of being removed from the reconfigurable resources; when the same tasks reappear, computation can be directly carried out, so that the configuration frequency is decreased and the reconfiguration expenditure is lowered. Even though the probability of reuse of the tasks can be increased by retaining the configuration of the completed tasks on the reconfigurable resources, idle resources of the reconfigurable resources can be reduced at the same time. When new tasks arrive, if the idle resources are not enough, the sizes of the partitions are modified according to certain conditions; if the idle resources are still not enough, one or more retained tasks are selected from the partition where the tasks at the lowest significance level are placed, and the retained tasks are replaced by the new tasks.

Description

technical field [0001] The invention relates to the field of reconfigurable computing, in particular to a dynamic reconfigurable task scheduling method. Background technique [0002] Reconfigurable computing refers to the use of systems integrated with programmable hardware for computing, and the functions of programmable hardware can be defined by a series of physically controllable points that change at regular intervals, and the computing hardware structure can be changed (reconfigurable). Reconfigurable computing not only maintains the traditional hardware-based execution efficiency, but also maintains a variable architecture, which can adapt to the diverse needs of practical applications. The performance between ASICs, thus having stronger computing power, has been widely used in many fields such as scientific computing, national defense and military, aerospace, etc., to achieve such as target matching, large numerical calculations, data mining, model simulation, etc. ...

AI Technical Summary

Problems solved by technology

Generally speaking, the task configuration process is often accompanied by delays, and the configuration process also brings a large amount of data access, which brings a lot of energy consumption to the FPGA

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