Three-dimensional semiconductor device and manufacturing method thereof

Abstract

The invention discloses a three-dimensional semiconductor device which comprises multiple storage units. Each storage unit comprises a channel layer, multiple interlayer insulating layers, multiple grid electroconductive layers, a grid dielectric layer, a drain electrode and a source electrode, each channel layer is distributed along a direction perpendicular to the surface of a substrate, the interlayer insulating layers and the grid electroconductive layers are alternately stacked along the side wall of the corresponding channel layer, each grid dielectric layer is positioned between the interlayer insulating layers and the side wall of the corresponding channel layer, each drain electrode is positioned at the top of the corresponding channel layer, each source electrode is positioned in the substrate between two adjacent storage units, and multiple second grid dielectric layers and multiple second channel layers are further arranged around each storage unit. According to the three-dimensional semiconductor device and a manufacturing method thereof, a current passage formed by stacking auxiliary MOSFET strings (metal oxide semiconductor field effect transistor) is formed around a vertical channel, and on-state current and electrorheology of storage strings are increased effectively, so that reading current and reading speed of a storage array are increased.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, a multilayer stack structure (for example, a plurality of ONO structures alternating with oxides an...

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Problems solved by technology

However, due to the large number of storage strings in the polysilicon vertical channel, for example, usually 14 stacked MOSFET structures, the on-off current and current ratio are small, resulting in small read current and low read speed, which cannot be applied to high-speed applications. Density, high-speed memory cells

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