NOR flash memory and manufacture method thereof

Abstract

The invention discloses a NOR flash memory. In the flash cell array of the storage area of the NOR flash memory, active regions are in strip shapes and are arranged in parallel. The polycrystalline silicon of polycrystalline silicon control gates of the flash cells in the same row are connected together to form a polycrystalline silicon row. A polycrystalline silicon floating gate is on top of theactive region perpendicularly intersecting the polycrystalline silicon row and is isolated by a first gate oxide layer. A drain region comprises a self-aligned conformal injection region extending tothe sides of the active regions. The position of the self-aligned conformal injection region is defined by the self-aligned etched back field oxygen. The self-aligned etch back region of the field oxide is formed by the self-aligned definition of the gate structure and the active region after the gate structure etching. In the source region, a self-aligned conformal injection region is also superimposed. The invention also discloses a method for manufacturing a NOR flash memory. The NOR flash memory can improve the programming efficiency without changing the gate structure, and can also reduce electric leakage and improve the performance of the device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a NOR flash memory (Flash), and also relates to a manufacturing method of the NOR flash memory. Background technique [0002] Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrical programmability and erasability. At present, flash memory cells are mainly implemented at the 65nm technology node. With the demand for large-capacity flash memory, the number of chips on each silicon wafer will be reduced by using the existing technology nodes. At the same time, the increasing maturity of new technology nodes also promotes the production of flash memory cells with high-node technologies. [0003] Existing flash memory cells usually use hot electron injection to achieve programming. Hot electron injection is to turn on the channel by applying high voltage to the gate, an...

AI Technical Summary

Problems solved by technology

However, due to the large physical thickness of high-dielectric materials, while increasing the coupling rate of flash memory cells, it will increase the coupling between adjacent flash memory cells and increase the crosstalk of flash memory

Moreover, the floating gate area of ​​the fin structure is larger, which will also increase the coupling between flash memory cells.

Although different crystal planes can improve its programming speed, it still cannot eliminate the mutual interference between its flash memory cells, and this problem will become more serious as it continues to shrink

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