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An anti-latch trigger circuit for esd

A trigger circuit and anti-latch-up technology, which is applied in the direction of emergency protection circuit devices, circuit devices, emergency protection circuit devices, etc. for limiting overcurrent/overvoltage, can solve the problem of not being able to maximize the current discharge capacity of the SCR structure, and not being able to Taking into account issues such as latch-up effects to maximize the SCR current capability and reduce the trigger voltage

Inactive Publication Date: 2016-08-31
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This creates a contradiction. If you want a strong ESD current discharge capability, you cannot take into account the latch-up effect.
If you want to take into account the latch-up effect, the general approach is to increase the holding voltage of the SCR, but this will not maximize the current discharge capacity of the SCR structure

Method used

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  • An anti-latch trigger circuit for esd
  • An anti-latch trigger circuit for esd
  • An anti-latch trigger circuit for esd

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0025] Such as figure 2 As shown, this example includes detection circuit 1, output stage circuit 2 and SCR device connected in sequence; wherein, the detection circuit is composed of capacitor C11 and resistor R12; the power supply VDD is grounded to GND through capacitor C11 and resistor R12 in turn; the output stage circuit is composed of diode D21, D22, and D23; the anode of diode D21 is connected to the power supply VDD through C11, and its cathode is connected to the anode of diode D23; the cathode of diode D23 is connected to the anode of diode D22; the cathode of diode D22 is connected to the anode of diode D21; the gate of the SCR device Pole connected to the cathode of diode D21.

[0026] This example works as follows:

[0027] When the rising edge of the ESD pulse occurs on VDD, the pulse charges the upper plate of capacitor 11 . The charging current path at this time is as Figure 5 shown. When the current passes through the resistor 12, a voltage drop occurs ...

Embodiment 2

[0036] Such as image 3 As shown, the difference from Embodiment 1 is that a diode 13 is connected in parallel next to the resistor 12 in this example. The anode of the diode is connected to the lower plate of the capacitor 11, and its cathode is connected to GND. Other structures in the circuit remain unchanged.

[0037] Its working principle is basically the same as that of Embodiment 1, the difference is that this example uses a diode 13 to conduct the current when charging the capacitor 11 . Because the anode of the diode 13 induces a high potential when the capacitor 11 is rapidly charged to trigger the SCR. Therefore, the width-to-length ratio of the diode 13 is preferably less than 1.

[0038] Embodiment 2 sees the emulation diagram during normal power-on and the emulation diagram during ESD Figure 9 and Figure 10 .

Embodiment 3

[0040] Such as Figure 4 As shown, the difference from Embodiment 2 is that the diode 13 in Embodiment 2 needs to be reversely connected. That is, the cathode of the diode 13 is connected to the lower plate of the capacitor 11, the anode is connected to GND, and other structures in the circuit remain unchanged.

[0041] Its working principle is basically the same as that of Embodiment 2, except that the diode 13 is used in this example to provide the current path at the time of forward charging of the capacitor, while Embodiment 3 is just the opposite. The current path at the forward moment of the current is provided by the resistor 12, and the diode 13 only provides the capacitor discharge path. Since the circuit needs to output a higher negative potential when the capacitor is discharged, the width-to-length ratio of the diode 13 is also preferably less than 1.

[0042] Embodiment 3 sees the emulation diagram during normal power-on and the emulation diagram during ESD Figu...

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Abstract

The invention relates to electronic circuit technology, in particular to an anti-latch trigger circuit for ESD. The circuit of the present invention includes a detection circuit 1, an output stage circuit 2 and an SCR device connected in sequence; wherein, the detection circuit is composed of a capacitor C11 and a resistor R12; the power supply VVD is grounded to GND through the capacitor C11 and the resistor R12 in turn; the output stage circuit is composed of a diode D21 , D22, D23; the positive pole of diode D21 is connected to the power supply VDD through C11, and its negative pole is connected to the positive pole of diode D23; the negative pole of diode D23 is connected to the positive pole of diode D22; the negative pole of diode D22 is connected to the positive pole of diode D21; the gate pole of SCR device Connect to the cathode of diode D21. The beneficial effects of the present invention are that the maximization of the SCR current capacity has a significant effect on reducing the SCR trigger voltage, and at the same time, the circuit can capture the falling edge of the ESD pulse and output negative voltage to turn off the SCR structure. The invention is especially suitable for an ESD anti-latch trigger circuit.

Description

technical field [0001] The invention relates to electronic circuit technology, mainly used for electrostatic discharge (Electro Static Discharge, referred to as ESD for short) protection technology, specifically a kind of can identify the falling edge of ESD pulse and output closing signal to turn off the clamping device , Prevent latch-up (Latch-up) trigger circuit. Background technique [0002] ESD stands for Electrostatic Discharge, which is a common phenomenon in nature. ESD exists in every corner of people's daily life. But it is such a common electrical phenomenon that is a fatal threat to sophisticated integrated circuits. [0003] With the improvement of integrated circuit manufacturing technology, its minimum line width has dropped to submicron or even nanometer level. While improving chip performance, its ability to resist ESD is also greatly reduced, so electrostatic damage is more serious. The contradiction between process development and chip ESD resistance h...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02H9/04
Inventor 乔明齐钊马金荣薛腾飞张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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