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Memory control circuit

A technology for controlling circuits and memory, applied in memory systems, instruments, data processing power supplies, etc., can solve the problem of increased memory power consumption and achieve the effect of reducing power consumption

Inactive Publication Date: 2014-10-15
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the related art memory control circuit for supplying power to all memories, there is a problem that the power consumption of the memories becomes large because the power is equally supplied even to the memories that are not being accessed

Method used

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Embodiment Construction

[0029] Hereinafter, embodiments will be explained in more detail with reference to the accompanying drawings. The same reference numerals will be attached to the same or corresponding parts, and explanations thereon will not be repeated in some cases.

[0030]

[0031] figure 1 is a block diagram showing the configuration of a microprocessor according to an embodiment. Such as figure 1 As shown, the microprocessor 1 includes a CPU (Central Processing Unit) 2 , a non-volatile memory 3 , a memory control circuit 4 and a power switch circuit 5 .

[0032] The CPU 2 sequentially fetches instructions (fetch codes CD) contained in the program stored in the nonvolatile memory 3 (instruction fetch), and executes the fetched instructions. Normally, the CPU 2 outputs the memory address AD stored in a register called a program counter to the nonvolatile memory 3, and the instruction stored in the relevant memory address AD is read out. According to the operand address and / or operand...

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PUM

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Abstract

The memory power consumption is reduced more than in the past by performing a power control suitably for a nonvolatile memory. A memory control circuit is provided with a first register group for a CPU to perform separately initial setting of the operation mode (power OFF, standby, and power ON) of plural banks included in a nonvolatile memory, for every task of a program executed by the CPU, and an access determination unit which determines a bank to which an access from the CPU takes place, on the basis of the access address for instruction fetching and the kind of the fetched instruction. The memory control circuit switches the operation mode of each of the banks on the basis of the setting value of the first register group, and the determination result of the access determination unit.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2013-076689 filed on Apr. 2, 2013, including specification, drawings and abstract, is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates to a memory control circuit, and is suitably used to control, for example, a nonvolatile memory configured with a plurality of banks. Background technique [0004] In the related art memory control circuit for supplying power to all memories, there is a problem that the power consumption of the memories becomes large because power is equally supplied even to the memories that are not being accessed. In order to deal with such a problem, a memory control circuit in which a memory is divided into banks has been developed, and the memory control circuit suppresses power supply to banks that are not accessed. [0005] For example, in the memory device disclosed by Japanese Published Un...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/32G06F3/06
CPCG06F1/3234G06F1/3225G06F1/3275G06F13/1694Y02D10/00Y02D30/50G06F1/3206G06F3/0634G06F12/0646G06F2212/1028
Inventor 关诚司林越正纪中木村清
Owner RENESAS ELECTRONICS CORP