Process method for reducing floating gate holes

Abstract

The invention provides a process method for reducing floating gate holes. The process method at least comprises the following steps: at first, a liner oxide layer and a silicon nitride layer are deposited successively on an active region of a semiconductor substrate; secondly, the liner oxide layer, the silicon nitride layer and the active region are etched to form at least two inverted trapezoidal trenches, wherein the trenches do not penetrate through the active region; then, the trenches are filled with an insulating medium material to form shallow trench isolation regions; then, the selective etching process is adopted to etch the silicon nitride layer located between the shallow trench isolation regions, and at the same time, partial shallow trench isolation regions are etched to acquire a rectangular or inverted trapezoidal floating gate preparation region; and finally, a floating gate is prepared and formed in the floating gate preparation prepare. Thus, no hole will occur in the floating gate prepared and formed in the rectangular or inverted trapezoidal floating gate preparation region to avoid the floating gate from being failed, so the device reliability can be enhanced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a process method for reducing floating gate holes. Background technique [0002] As a main non-volatile storage device, flash memory (Flash) has been widely used in various portable electronic products such as U disk drives, MP3 players, digital cameras, personal digital assistants, mobile phones and laptop computers. Memory with storage capacity, low cost and low power consumption has become the development trend of non-volatile memory. The NOR flash device is a kind of non-volatile flash memory. At present, the NOR flash device adopts the self-aligned floating gate process, and its preparation process is as follows: figure 1 with figure 2 Shown: [0003] In the first step, a pad oxide layer 2A and a silicon nitride layer 3A are sequentially deposited on the active region 1A of the semiconductor substrate; [0004] The second step is to etch the pad oxide layer 2A...

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Problems solved by technology

[0008] Since the remaining silicon nitride layer 3A has a trapezoidal structure after etching the pad oxide layer 2A, silicon nitride layer 3A and active region 1A in step 2), the shallow trench is etched in step 4). The silicon nitride layer 3A between the isolation regions 5A, the floating gate to-be-prepared region 6A obtained also has a trapezoidal structure, and the floating gate to-be-prepared region 6A of this trapezoidal structure will cause holes to be generated in the subsequently deposited floating gate 7A, Make the device open circuit or even invalid, in this way, the reliability of the device will be seriously affected

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