FPGA hardware abstraction layer based on serial high-speed bus and its realization method
A serial high-speed bus, hardware abstraction layer technology, applied in the field of hardware abstraction layer implementation, can solve the problems of application software portability, poor operability and reusability, etc.
Active Publication Date: 2017-03-22
CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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[0008] The purpose of the present invention is to provide a kind of design method based on MHAL on the FPGA of serial high-speed bus, when all FPGA hardware platforms in the software radio system based on serial high-speed bus all use this MHAL, user or communication assembly (hereinafter referred to as HC) can conveniently communicate within the system by using the unified interface provided by MHAL, and can freely transplant programs between FPGAs of different models and specifications, which solves the problem of FPGA applications in software radio systems based on serial high-speed buses. Poor software portability, operability and reusability
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[0054] An embodiment and steps of the present invention are given below.
[0055] Image 6 It is a block diagram of the system of the example. The whole system mainly includes two FPGA development boards with one XC5VFX70T FPGA and optical module, and two optical fiber cables for sending and receiving. Use two optical fiber cables to interconnect the transceiver ports of the optical modules of the two boards, and load the MHAL program in each FPGA. Next, use these two FPGAs to communicate with each other through the serial high-speed bus through MHAL, and monitor all ports of the FPGA through Xilinx's ChipScope software.
[0056] The first step is to configure the device address:
[0057] 1) The user program pulls up the DEVICE_ID_EN interface of MHAL, and writes the device address 0x53 through the DEVICE_ID interface;
[0058] 2) Monitor whether the SET_ID_DONE pin of MHAL is high through ChipScope software, and high indicates that the device address is written successful...
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The invention discloses an FPGA hardware abstraction layer based on a high-speed serial bus. With an IP core of the high-speed serial bus provided by an FPGA manufacturer as an external interface, and internal uniform interfaces are provided for users or communication components for use. The FPGA hardware abstraction layer comprises an IRESP module, an IREQ module, a DATA_CTRL module and a TREQ module which all serve as functional modules. The invention further discloses an implement method of the FPGA hardware abstraction layer. Thus, the users or communication components can perform communication in a system through the uniform interfaces provided by the hardware abstraction layer, programs can be freely transplanted between different models and specifications of FPGAs, and the problem that in a software radio system based on the high-speed serial bus, the portability, the operability and the reusability of application software of the FPGAs are poor is solved.
Description
technical field [0001] The invention relates to a hardware abstraction layer design method of a hardware platform under a serial high-speed bus architecture, in particular to an implementation method of a hardware abstraction layer (hereinafter referred to as MHAL) based on FPGA (Field Programmable Logic Array). Background technique [0002] Different communication modes and functions in wireless communication use different working frequency bands, modulation methods, communication protocols and encryption methods, etc. These differences limit the connectivity between different communication devices and bring inconvenience. The idea of software radio is based on a common, standard, modular hardware platform, and realize various functions of radio stations through software programming. [0003] MHAL is between the hardware platform and the software. In order to shield the hardware differences, it abstracts the hardware implementation, is responsible for dealing with the dif...
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IPC IPC(8): G06F17/50
Inventor 羿昌宇沈聪李裕吴敏
Owner CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST