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Small Footprint Semiconductor Packages

A technology for semiconductors and semiconductor tubes, applied in the field of semiconductor packaging, can solve problems such as dissipation and increased cost

Active Publication Date: 2018-03-13
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Many 'squares' (i.e. 1 mm² cells) are required on the surface of the PCB to accommodate such source-down or drain-down package configurations, which increases the cost of the package
Furthermore, the heat dissipated at the main surface of the die facing the substrate is at least partially dissipated through the PCB / substrate
Conventional PCBs must therefore provide both electrical and thermal paths for components mounted on the PCB, resulting in a large number of components sharing the thermal path of the designed PCB

Method used

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  • Small Footprint Semiconductor Packages
  • Small Footprint Semiconductor Packages
  • Small Footprint Semiconductor Packages

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] Embodiments described herein provide a semiconductor package for mounting to a PCB or other type of substrate such that a semiconductor die included in the package faces the substrate at its edge rather than the edge of the die. Mounted with either major surface facing the substrate. Such a configuration results in a small package footprint and greater heat dissipation at both main surfaces of the die. Various embodiments described next relate to semiconductor packages themselves, semiconductor assemblies including such packages, and methods of manufacturing the packages. The semiconductor die included in the package can be any type of semiconductor die such as IGBT (Insulated Gate Bipolar Transistor) die, power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) die, JFET (Junction Field Effect Transistor) die, ) die, GaN die, SiC die, thyristor die, power diode die, power integrated circuits, etc. A semiconductor die typically has a current flow path from one...

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PUM

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Abstract

A small footprint semiconductor package is disclosed. A semiconductor assembly includes a substrate having conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a molding compound. The die has opposing first and second major surfaces, an edge disposed perpendicular to the first and second major surfaces, a first electrode at the first major surface, and a first electrode at the second major surface the second electrode at the major surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The molding compound surrounds the die and at least a portion of the first and second terminals such that each of the terminals has a side parallel to and facing away from the die, the side remaining at least partially free covered by the molding compound. The first terminal and the second terminal of the semiconductor package are connected to different ones of the conductive regions of the substrate.

Description

technical field [0001] This application relates to semiconductor packages, and more particularly, to semiconductor packages having a small footprint. Background technique [0002] Conventional high power semiconductor packages with semiconductor dies (chips) require relatively large PCB (printed circuit board) footprints. Both major surfaces of the die typically have one or more electrodes. The die is attached to the PCB with one major surface facing the PCB and the other major surface facing away from the PCB. Each electrode provided at the facing surface of the die is attached to a corresponding conductive region of the PCB, for example in a source-down or drain-down configuration. Metal clips or other connecting elements such as bonding wires or straps extend from the PCB to the other main surface of the die to make electrical connection with each electrode provided at the surface of the die facing away from the PCB. Many 'squares' (ie 1 mm2 cells) are required on the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/367H01L23/48H01L21/50
CPCH01L2924/13062H01L2924/1306H01L2924/1301H01L2924/13055H01L2924/13091H01L2924/1305H01L23/051H01L23/36H05K1/0209H05K1/181H05K2201/10166H05K2201/10454H01L2924/181H01L2224/73151H01L2224/08237H01L2224/80898H01L24/05H01L24/06H01L24/08H01L24/27H01L24/29H01L24/30H01L24/32H01L24/33H01L24/73H01L24/80H01L24/83H01L24/92H01L2224/06181H01L2224/06183H01L2224/293H01L2224/32245H01L2224/33181H01L2224/83191H01L2224/83815H01L2224/922H01L2224/9221H01L2924/15153H01L2924/15159H01L2224/29294H01L2224/30181H01L2224/04H01L2224/08257H01L2224/73251Y02P70/50H01L23/492H01L2924/00H01L2224/27H01L2224/83H01L2924/00014H01L2924/014H01L2224/05H01L2224/29H01L2224/80H01L2924/00012H01L23/34H01L24/81H01L25/065
Inventor 龙登超陈天山
Owner INFINEON TECH AG