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A method for adjusting the hierarchical structure of small cells in integrated circuit layout verification

A graphic structure adjustment and hierarchical structure technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem that the layout hierarchical structure affects verification efficiency, etc., to maintain data structure and integrity, and improve hierarchical processing efficiency Effect

Active Publication Date: 2017-11-14
北京华大九天科技股份有限公司
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Problems solved by technology

[0004] Aiming at the problem that layout hierarchy affects verification efficiency faced in integrated circuit layout design, the present invention proposes a small unit hierarchy adjustment method in integrated circuit layout verification in combination with graphic segmentation and search methods

Method used

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  • A method for adjusting the hierarchical structure of small cells in integrated circuit layout verification
  • A method for adjusting the hierarchical structure of small cells in integrated circuit layout verification
  • A method for adjusting the hierarchical structure of small cells in integrated circuit layout verification

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Embodiment Construction

[0011] The processing flow of this method is as follows figure 1 shown. Introduce the concrete implementation of this method below in conjunction with example, as figure 2 Shown is an example layout where the cell top( figure 2 (1)) is the top-level unit, including subunit a( figure 2 (2)), subunit b( figure 2 (3)). Among them, subunit b is a qualified small unit, subunit a is not a small unit and subunit a is the only instance in the layout. The hierarchical relationship of the layout after the hierarchical adjustment method is as follows: image 3 shown. The following combination figure 2 The example shown describes the specific steps of the method:

[0012] Step 1: first traverse the layout hierarchical units, and select subunit a as a candidate target unit. Record the border information of a (for example, by means of two-dimensional buckets). Secondly, according to the area of ​​the cell border, it is determined that the subunit b is a small unit, which meet...

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Abstract

The invention discloses a graphic structure adjustment method in integrated circuit layout verification, and belongs to the technical field of computer-aided design of integrated circuits, especially the design rule check (DRC) field of integrated circuit layout. The basic steps of this method are as follows: firstly, the unit selection method is used for the small hierarchical units that meet certain conditions in the layout, and the target hierarchical units and source hierarchical units for hierarchical structure adjustment are selected. Secondly, the cell structure adjustment method is used to adjust the hierarchical structure of the selected source cells and target cells to optimize the layout hierarchy and further optimize the verification of layout rules.

Description

technical field [0001] The invention relates to a method for adjusting the hierarchical structure of a very small unit in integrated circuit layout verification, and belongs to the technical field of computer aided design of integrated circuits, in particular to the field of design rule checking (DRC) of integrated circuit layout. Background technique [0002] With the development of integrated circuit technology, the feature size of the chip is getting smaller and smaller, the integration level of a single chip is constantly improving, the structure and process are becoming more and more complex, and the scale of the layout database is increasing exponentially. With the expansion of chip scale, the design rules that need to be verified in each stage of integrated circuit design are also increasing. Among them, design rule checking (DRC) of integrated circuit layout becomes more and more important, and they play an important role in reducing design errors, design costs and d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 张路马海南李志梁
Owner 北京华大九天科技股份有限公司
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