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Parameter testing method aiming at memory devices of capacitor structure and MOS tube structure

A MOS structure and parameter testing technology, applied in static memory, instruments, etc., can solve the problems of separate programming and erasing operations, inability to automatically extract parameters of capacitor structure devices and four-terminal MOS structure devices, and inability to automate device testing, etc. Achieve the effect of improving test efficiency and speeding up extraction

Inactive Publication Date: 2014-12-24
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At present, in the process of analyzing the characteristics of this new type of device in the laboratory, because the dedicated semiconductor parameter analyzer only provides separate programming and erasing operations, it is impossible to perform automated testing of the device
Even if some devices have certain automation functions, due to their limitations in programming and erasing conditions, it is still impossible to automatically extract parameters for capacitor structure devices at both ends and four-terminal MOS structure devices

Method used

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  • Parameter testing method aiming at memory devices of capacitor structure and MOS tube structure
  • Parameter testing method aiming at memory devices of capacitor structure and MOS tube structure
  • Parameter testing method aiming at memory devices of capacitor structure and MOS tube structure

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Embodiment Construction

[0061] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0062] The present invention provides a parameter testing method for storage devices with capacitor structure and MOS tube structure, wherein the two-terminal storage device is a device with a capacitor structure, and the four-terminal storage device is a device with a MOS tube structure. The method of the main parameters such as the programming speed, erasing speed and endurance parameters of the charge trap memory device (CTM). For devices with capacitive structures, this method can program or erase the device to a specified flat-band voltage (Vfb), and test the variation curve of the flat-band voltage of the device with the programming or erasing voltage and programming or erasing time ( That is, the speed curve); and ...

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Abstract

The invention discloses a parameter testing method aiming at memory devices of a capacitor structure and an MOS tube structure. Aiming at the device of the capacitor structure, the method comprises the following steps: programming the device or erasing the device to be close to appointed flat band voltage Vfb; testing a changing curve of the flat band voltage along with programming or erasing voltage and programming or erasing time to obtain a programming speed and an erasing speed; and testing a changing curve of the flat band voltage of the device under appointed programming and erasing conditions along with programming and erasing times to obtain a tolerance parameter. Aiming at the memory devices of the MOS structures at the four ends, the method comprises the following steps: programming or erasing the devices to appointed threshold value voltage Vth and testing a changing curve and a tolerance curve of the threshold value voltage along with programming or erasing voltage and programming or erasing time to obtain a programming speed, an erasing speed and a tolerance parameter.

Description

technical field [0001] The invention relates to the testing field of semiconductor memory, in particular to a parameter testing method for storage devices with capacitance structure and MOS transistor structure. Background technique [0002] Since D.Kahng and S.M.Sze of Bell Labs first proposed the floating gate MOS transistor storage structure (Flash) in 1967, non-volatile semiconductor memory has been widely developed and applied. The working principle of this structure is to add a layer of floating gate between the control gate and the conductive channel of the MOS transistor, and modulate the turn-on threshold voltage of the MOS transistor by controlling the amount of charge on the floating gate, which is represented by the threshold voltage Threshold information. [0003] Applying appropriate excitation voltage to the gate, source, drain and substrate of the floating gate type MOS can inject electrons into the floating gate, or drive electrons out of the floating gate,...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/08
Inventor 余兆安姚志宏霍宗亮龙世兵谢常青刘明
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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