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QSYS system based image processing abnormal monitoring method and system

An image processing and abnormal technology, applied in the field of image processing, can solve problems such as imperfect filter function of IP module, non-intelligent, IP module cannot recover by itself, etc.

Inactive Publication Date: 2014-12-24
GUANGDONG VTRON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, under this mechanism, there is a problem that in some extremely abnormal situations, for example, when the video signal source resolution is switched or the signal source is plugged and unplugged, the decoding chip will occasionally output some extremely abnormal resolution images. The image data enters the FPGA chip, then enters the QSYS system, and reaches some IP modules for processing. Due to problems such as troubleshooting or imperfect filtering functions of the IP module itself, the IP module enters a state that cannot be recovered by itself, that is, "hanging dead". Status", on the display, it shows that the screen is stuck or the screen is blurred. Since the IP module is provided by the manufacturer, it is equivalent to a "black box" for developers, and the internal code of the IP module cannot be modified and debugged. to solve the above problems
In actual application, the image can only be restored to normal by manually resetting or restarting the device; this method is quite mechanical and unintelligent, and because it is not targeted, it will waste a lot of time and the image restoration efficiency is low. For some important applications Occasions, such as monitoring or demonstration occasions, are quite a serious problem

Method used

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  • QSYS system based image processing abnormal monitoring method and system

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Experimental program
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Embodiment 1

[0035] see figure 2 As shown, it is a schematic flowchart of Embodiment 1 of the method for monitoring abnormal image processing based on the QSYS system of the present invention. like figure 2 As shown, the monitoring method for abnormal image processing based on the QSYS system in this embodiment includes the following steps:

[0036] Step S201: Detect whether the target signal in the Avalon ST data stream signal of the current IP module of the QSYS system is low level, if so, enter step S202;

[0037] Among them, the target signal includes any one or more signals in any of the above-mentioned data_valid, sop, eop, and st_ready, but in order to facilitate detection, it is generally selected to detect one of the signals in data_valid, st_ready;

[0038] Step S202: Timing the time when the target signal is at a low level to obtain a duration, and when the duration is greater than a preset time threshold, enter step S203;

[0039] Start timing when the target signal is detec...

Embodiment 2

[0047] see Figure 4 As shown, it is a schematic flowchart of Embodiment 2 of the method for monitoring abnormal image processing based on the QSYS system of the present invention. In this embodiment, the target signal is the st_ready signal, and based on the detection of the st_ready signal, the judgment of whether the IP module is in the hang-up state is implemented as an example for illustration.

[0048] Considering that when the IP module of the ST stream link is running normally, the st_ready signal is at a high level most of the time, even if no video signal is input to the QSYS system, the st_ready signal will always remain at a high level, and it is always waiting The state of receiving data, when the IP module is not ready to receive data during the operation process, the st_ready signal becomes low level for a short time (up to 200 milliseconds in the case of passing), and when the internal operation processing is completed, the st_ready signal It will automaticall...

Embodiment 3

[0058] see Figure 5 As shown, it is a schematic flowchart of Embodiment 3 of the method for monitoring abnormal image processing based on the QSYS system of the present invention. The difference between the present embodiment and the second embodiment is that the target signal is the data_valid signal, and based on the detection of the data_valid signal, the judgment of whether the IP module is in the hang-up state is implemented as an example for illustration.

[0059] like Figure 5 As shown, the monitoring method for abnormal image processing based on the QSYS system in this embodiment includes the following steps:

[0060] Step S401: Obtain the information of whether the QSYS system has a signal source input by reading the decoding chip. If there is a signal source input, check whether the data_valid signal output from the IP module of this level to the IP module of the next level is low level, if it is low level, enter the step S402;

[0061] In this embodiment, befor...

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Abstract

The invention provides a QSYS system based image processing abnormal monitoring method and system. The method includes: detecting whether a target signal of an Avalon ST (Avalon streaming interface) of a corresponding IP (intellectual property) module of the QSYS system is low level or not; if so, timing the time of the target signal as the low level to acquire the duration time; when the duration time is larger than a preset time threshold, subjecting the corresponding IP module to restoration operation. By the method and system, the suspended state of the IP module of the QSYS system can be instantly detected, and image restoration efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of image processing, in particular to a monitoring method and system for abnormal image processing based on a QSYS system. Background technique [0002] In the field of image processing technology, the image data is collected through the decoding chip, and then the FPGA (Field Programmable Gate Array, Field Programmable Gate Array) chip is used as the data processing center to cache the image data or perform algorithmic operations, and then the MCU (Single Chip Microcomputer, single-chip microcomputer) or CPU (Central Processing Unit, central processing unit) as the control center controls the FPGA chip and peripheral circuits to work normally, and finally makes the image data normally output to the display for display. more and more common. At present, Altera, as a large manufacturer of FPGA chips, provides a development platform based on the QSYS system (the QSYS system was formerly known as the SOPC syst...

Claims

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Application Information

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IPC IPC(8): H04N17/00
Inventor 陈燕凯曹捷林文富
Owner GUANGDONG VTRON TECH CO LTD
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