On-line error detection circuit for fault of NoC (Network-on-Chip) illegal path

Abstract

The invention discloses an on-line error detection circuit for the fault of an NoC (Network-on-Chip) illegal path. The on-line error detection circuit is arranged at each receiving port of an NoC router; corresponding to different input ports of an on-chip router at the same level, a tag updating unit is used for updating an on-chip network data package head part so as to record an identifier of a previous router input port and provide input terminal information of the on-chip router at the same level for a next error detection unit; and according to relative position information of a data package destination and a present data package position, a fault on-line error detection circuit is used for judging whether an on-chip network data package received by an input terminal of the NoC is influenced by a fault of a control path of a previous NoC router, is sent to an error port and generates an illegal path. The on-line error detection circuit can effectively recognize a data package which is transmitted to a wrong direction and generates an illegal path due to a control logic error. The on-line error detection circuit fully utilizes present computing resources in the router, can realize parallel processing with normal process of the router, and does not influence the performance of the router.

Description

technical field [0001] The invention relates to fault detection of a two-dimensional on-chip network router, in particular to an on-chip network illegal path fault on-line error detection circuit. Background technique [0002] The commonly used two-dimensional network-on-chip router architecture with virtual channels is shown in Figure 1, which includes five input and output physical ports of east, south, west, north and local interfaces, as shown in Figure 2. In addition to the local interface, each other input port can contain several virtual channels (virtual channel, VC). This router contains 5 processing steps, namely routing computation (routing computation, RC), virtual channel president (virtual channel allocator, VA), switching arbitration (switch allocation, SA), switching transmission (switch traversal, ST) and output Transmission (link traversal, LT). Among them, the routing calculation unit unpacks the input data packet, analyzes the source address and des...

AI Technical Summary

Problems solved by technology

However, its disadvantage is that before each forwarding, it is necessary to obtain prior information on whether each router on the relevant path is faulty, and then select an appropriate path for the data packet to bypass the faulty router.

This method greatly reduces the operating efficiency of the network and is not suitable for high-speed on-chip networks

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