Address mapping algorithm for transposed matrix based on single-port SRAM

Abstract

The invention belongs to the technical field of high-definition digital video compression coding and decoding and particularly relates to an address mapping algorithm for a transposed matrix based on a single-port SRAM in a 2D-DCT/IDCT under HEVC video coding standards. The address mapping algorithm is based on the algorithm of transposition of matrix blocks, that is, the matrix is divided into blocks first, the whole matrix and small-sized matrix blocks are transposed with the small-sized matrix blocks and basic elements as units, and transposition of the small-sized matrix blocks can be achieved directly by means of ranking. The algorithm is implemented on the basis of transform units (TUs) and supports four sizes of the TUs allowed by the HEVC, the fixed throughput rate 32 pixes/cycle can be realized, and the method is applicable to the 2D-DCT/IDCT with a high throughput rate and a high-performance video coder and decoder. According to the algorithm, by means of a hardware structure, the area can be reduced by 40% or so; compared with an existing address mapping algorithm for the transposed matrix based on the single-port SRAM, the algorithm has the advantages that on the condition of not increasing hardware expenses, a higher throughput rate can be obtained, and real-time coding of high-definition videos can be achieved.

Description

technical field [0001] The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and is aimed at the HEVC video encoding and decoding standard, and specifically relates to an address suitable for the 2D-DCT / 2D-IDCT transposition matrix in a video encoder and a decoder under the HEVC video encoding standard Mapping algorithm. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard H.264 / AVC under the premise of the same visual effect. In order to achieve the goal, the computational complexity of HEVC is greatly increased compared with H.264, so the hardware overhead and power consumption of the HEVC encoder and decoder are rela...

AI Technical Summary

Problems solved by technology

In the design of these 2D-DCT / IDCT, the transpose matrix is ​​based on the register array, the hardware overhead is large, and the movement of data in the register results in high power consumption

An address mapping algorithm based on the transposition matrix of single-port SRAM has been proposed, but this algorithm is only suitable for low-throughput 2D-DCT / IDCT architectures

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