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A reconstructed loop structure suitable for full multiplexing in encoders under hevc standard

An encoder and standard technology, applied in digital video signal modification, electrical components, image communication, etc., can solve the problems of large hardware area, inability to realize full flow, impractical, etc., achieve high-efficiency real-time encoding, improve hardware utilization, The effect of small hardware overhead

Active Publication Date: 2017-12-01
FUDAN UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

The full parallel structure can realize the form of full pipeline, but the hardware area is too large, and the semi-multiplex structure can not realize the form of full pipeline although the area is low
Due to the correlation between data, the data will not be input continuously, and the fully parallel structure is not practical

Method used

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  • A reconstructed loop structure suitable for full multiplexing in encoders under hevc standard

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Embodiment Construction

[0015] The method of the present invention will be further specifically described below by way of examples and in conjunction with the accompanying drawings.

[0016] There are two control signals for rebuilding the loop structure: positive and negative selection signals, and row and column selection signals. The sequence of operations is as follows: When the positive and negative selection signal and the row and column selection signal are "00", the input data is subjected to row (column) discrete cosine transformation, and the intermediate result is stored in the transposed matrix; When the positive and negative selection signal and the row and column selection signal are "01", read out from the transposed matrix The intermediate results are subjected to column (row) discrete cosine transform, and the output results are quantized and stored in the coefficient memory. Read out the quantized result from the coefficient memory for inverse quantization, the positive and ne...

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Abstract

The invention belongs to the technical field of high definition digital video compression coding and decoding, and particularly relates to a reconstruction loop structure applicable to full multiplexing of an encoder under an HEVC (high efficiency video coding) standard. The reconstruction loop structure applicable to the full multiplexing of the encoder under the HEVC standard includes four portions of 2D-DCT (two dimension discrete cosine transformation), quantization, inverse quantization and 2D-IDCT (two dimension inverse discrete cosine quantization). The full multiplexing reconstruction loop structure is achieved by using the 2D-DCT and the 2D-IDCT and reusability of a quantization and inverse quantization structure and reusing a coefficient storage in the encoder. The reconstruction loop structure applicable to the full multiplexing of the encoder under the HEVC standard supports flow line type processing of a 32*32 luminance block, two 16*16 chromaticity blocks, a 16*16 luminance block and two 8*8 chromaticity blocks, and a 8*8 luminance block and two 4*4 chromaticity blocks. The reconstruction loop structure applicable to the full multiplexing of the encoder under the HEVC standard improves hardware usage rate by using a parallelism and flow line type processing mode, and can achieve fixed throughput rate of 32 pixel / cycle. The reconstruction loop structure applicable to the full multiplexing of the encoder under the HEVC standard can achieve a high performance reconstruction loop through low hardware spending, and thereby efficiently achieves real time coding of high definition video.

Description

technical field [0001] The invention belongs to the technical field of high-definition digital video compression encoding and decoding, and is aimed at the HEVC video encoding and decoding standard, and specifically relates to a reconstruction loop hardware structure suitable for full multiplexing in an encoder under the HEVC standard. Background technique [0002] HEVC (High Efficiency Video Coding) is a next-generation video codec standard proposed by JCTVC, an organization jointly established by the International Telecommunications Organization (ITU) and the Motion Picture Experts Group (MPEG). The goal is to double the compression rate compared to the previous generation standard H.264 / AVC under the premise of the same visual effect. [0003] The video encoder based on HEVC is mainly composed of the following modules: intra prediction, inter prediction, reconstruction loop, deblocking filter, adaptive sample compensation, entropy coding and other modules. The basic proc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/625H04N19/124H04N19/61
Inventor 范益波谢峥黄磊磊王利鸣曾晓洋
Owner FUDAN UNIV
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