Block-division low-power-consumption magnetic memory cache framework design method

Abstract

A block-division low-power-consumption magnetic memory cache architecture design method comprises four major steps: 1, a plurality of block modes with highest appearing frequency in L1 written-back data and L1 read data are subjected to statistics, then a mode table is composed, and an index value is correspondingly allocated; two, when a program runs, the pattern table is loaded to a special L1 level cache; when new data is read from an L2 level cache, a mode of the new data is calculated, and whether the mode of the new data is hit is examined in the mode table; three, when data needs to be written back to the L2 level cache, a mode of the data is again calculated, the mode is compared with a mode indicated by an index bit of a block, and a control bit is obtained; and four, when the data is written back to the L2, the control bit controls a writing operation of a corresponding sub block, if the control bit is 1, a written-back control signal of the data of the corresponding sub block is set to be valid, otherwise a writing enable of the corresponding sub block is invalid.

Description

technical field [0001] The invention relates to a low-power magnetic memory cache architecture design method for word block division. It divides the cache into sub-blocks, adds data change flag bits for the sub-blocks, and divides the sub-blocks into sub-blocks by identifying the flag bits. different categories. A magnetic memory architecture design method for reducing cache write energy consumption by optimizing write operations of different types of sub-blocks. It belongs to the technical field of magnetic memory and low power consumption design. technical background [0002] With the continuous improvement of process size, the integration level of on-chip transistors is getting higher and higher. In order to greatly improve processor performance under a given power consumption constraint, multi-core processors have begun to be widely used. As the number of cores increases, processors have greater and greater requirements for on-chip cache capacity and bandwidth. With ...

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Problems solved by technology

The data interaction between the on-chip cache and the processor core is the most frequent. If data needs to be frequently written to the cache during program execution, the power consumption of the on-chip cache based on STT-MRAM technology will be very large, which may offset the use of STT-MRAM. the benefits

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