A low-cost and high-bandwidth microprocessor instruction fetching method and its instruction fetching structure

Abstract

The invention provides an instruction fetching method and an instruction fetching structure thereof for a low-cost high-band-width microprocessor. The instruction fetching method comprises the following steps that firstly, a cache memory is divided into storage structures realizing parallel operation of a plurality of sub storage bodies; then, instructions for continuous instruction fetching are distributed into different sub storage bodies; if the starting address of an instruction fetching packet does not correspond to the first sub storage body in a cache line, a storage line mode spanning across the sub storage bodies is adopted for instruction fetching; the address self increase logics are set for other sub storage bodies except the tail sub storage body, and whether to access the current line or the next line of the sub storage body is determined according to the address of the current instruction fetching packet; finally, the instruction sequence regulating logics are set, for sub storage bodies except the tail sub storage body, instructions with the reverse sequence with the original instruction sequence due to cross-line access are sequentially regulated, and in addition, the final instruction sequence is sent to the processor in sequence. The invention also discloses an instruction fetching structure adopting the instruction fetching method, and the requirement of reading a plurality of instructions in a single period is met through fewer storage bodies.

Description

technical field [0001] The invention relates to an instruction fetching method and an instruction fetching structure of a microprocessor, in particular to a low-cost and high-bandwidth microprocessor fetching method and an instruction fetching structure. Background technique [0002] Modern microprocessors can achieve higher performance by simultaneously issuing and executing multiple instructions in one clock cycle, but the basic premise is that they need to be supported by a higher instruction fetch bandwidth, that is, they can be read from the instruction cache in a single cycle. Multiple instructions are read from and sent back to the pipeline for execution. Based on such bandwidth requirements, the instruction cache memory should theoretically provide multiple access ports. In the specific processor design, there are four realization technologies of multi-port cache: (1) Full custom design of multi-port SRAM. Since each additional port of the SRAM memory must correspo...

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Problems solved by technology

[0004] Aiming at the problems existing in the prior art, the present invention provides a method to achieve parallelization by using fewer cache memory banks and corresponding memory bank address self-increment logic, which is simple to control and low in cost, and can effectively solve the complex design of the prior art. A low-cost and high-bandwidth microprocessor instruction fetch method and its instruction fetch structure that meet the requirements of reading multiple instructions in a single cycle in high-performance processors

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