Verifying partial good voltage island structures
A technology of integrated circuits and logic blocks, applied in electrical digital data processing, CAD circuit design, digital data processing components, etc., can solve the problems of increasing chip design time and complexity, and unreasonable time consumption
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[0017] The present invention relates to integrated circuits, and more particularly to the design and verification of integrated circuits including redundant logic blocks. According to some aspects of the present invention, methods and related structures for integrated circuits are provided that allow control of logic segmentation verification for redundant logic blocks. That is, the work of verification is divided into items. Logic functional verification (leveraging normal functional logic simulation / coverage techniques) verifies basic building blocks (eg individual logic blocks). Structural verification verifies that the building blocks are correctly wired together at the chip level. Furthermore, aspects of the invention allow chip-level verification of redundant logic blocks using only one representative permutation, wherein one or more redundant logic blocks are disabled according to a partially good chip design. Accordingly, segment verification according to aspects of ...
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