Formation method of polysilicon gate

A polysilicon gate, polysilicon layer technology, applied in electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve problems such as poor performance and impact of semiconductor devices, and achieve the advantages of reducing line width roughness and reducing manufacturing costs. Effect

Active Publication Date: 2017-06-16
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the line width roughness (Line WidthRoughness, LWR for short) of the polysilicon gate 21 formed by the above method is relatively large, which has a bad influence on the performance of the semiconductor device.

Method used

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  • Formation method of polysilicon gate
  • Formation method of polysilicon gate
  • Formation method of polysilicon gate

Examples

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no. 2 example

[0066] The difference between the second embodiment and the first embodiment is that in the second embodiment, the method for forming the patterned mask layer includes: forming a hard mask layer on the polysilicon layer, The bottom anti-reflection layer on the layer and the photoresist layer on the bottom anti-reflection layer; the photoresist layer and the bottom anti-reflection layer are patterned; the patterned photoresist layer is used as a mask to The hard mask layer is etched to form the patterned mask layer; the patterned photoresist layer and bottom anti-reflection layer are removed.

no. 3 example

[0068] The difference between the third embodiment and the first embodiment is that in the third embodiment, the method for forming the patterned mask layer includes: forming a bottom anti-reflection layer on the polysilicon layer, and A photoresist layer on the reflection layer; patterning the photoresist layer and the bottom anti-reflection layer to form the patterned mask layer.

no. 4 example

[0070] The difference between the fourth embodiment and any of the first to third embodiments is that in the fourth embodiment, after the second anisotropic dry etching and before the third anisotropic dry etching , further comprising: removing the patterned mask layer.

[0071] In the above-mentioned first to third embodiments, after the third anisotropic dry etching, the patterned mask layer formed above the polysilicon gate has other uses in the subsequent process, so in the second anisotropic After the dry etching and before the third anisotropic dry etching, the patterned mask layer is not removed.

[0072] In the present invention, in the second anisotropic dry etching step, the temperature of the heating condition is not limited to the given embodiment, as long as the temperature is higher than room temperature.

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Abstract

The invention discloses a method for forming a polysilicon grid electrode. The method comprises providing a substrate; forming a polysilicon layer and a graphical mask layer on the polysilicon layer; using the graphical mask layer as a mask, performing first anisotropism dry etching on the polysilicon layer, so as to remove part thickness of the polysilicon layer, and forming the upper part of a polysilicon grid electrode; performing second anisotropism dry etching by using a gas containing H2 under a heating condition, so as to rimming the side wall of the upper part of a polysilicon grid electrode; and after the second anisotropism dry etching, performing third anisotropism dry etching on the polysilicon layer to remove the residual polysilicon layer under the polysilicon layer in part thickness, so as to form the polysilicon grid electrode. Using the method can reduce the line width roughness of the polysilicon grid electrode.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a polysilicon gate. Background technique [0002] Existing methods for forming polysilicon gates include: [0003] Such as figure 1 As shown, a substrate 1 is provided, and a polysilicon layer 2, a bottom anti-reflection layer (Barc) 3 located on the polysilicon layer 2, and a photoresist layer 4 located on the bottom anti-reflection layer 3 are formed on the substrate 1; [0004] Such as figure 2 As shown, for the photoresist layer 4 (as figure 1 shown) to be patterned to form a patterned photoresist layer 41, for the bottom anti-reflection layer 3 (such as figure 1 As shown), patterning is performed to form a patterned bottom anti-reflection layer 31; [0005] Such as image 3 As shown, with the patterned photoresist layer 41 as a mask, the polysilicon layer 2 (such as figure 2 As shown), etching is performed to form a polysilicon gate 21 . ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/3213
CPCH01L21/28035H01L21/32135H01L21/32139
Inventor 孟晓莹王冬江
Owner SEMICON MFG INT (SHANGHAI) CORP
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