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Method for improving functional verification efficiency of embedded processor

An embedded processor, functional verification technology, applied in functional inspection, detection of faulty computer hardware, etc., can solve problems such as difficult to find problem recurrence, redundant application scenarios, wasting time, etc., to shorten the time to market, improve Verify the effect of efficiency

Active Publication Date: 2015-03-25
CHIPSEA TECH SHENZHEN CO LTD
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  • Abstract
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Problems solved by technology

[0006] For so many verification platforms, building them independently will waste a lot of time and bring a lot of repetitive workload that could have been avoided. Some reusable methods that are currently widely circulated are not very effective in building real application scenarios, and are prone to some problems. Redundant application scenarios, and it is not easy to reproduce the problems found later

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  • Method for improving functional verification efficiency of embedded processor
  • Method for improving functional verification efficiency of embedded processor
  • Method for improving functional verification efficiency of embedded processor

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Embodiment Construction

[0045] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0046] Please refer to figure 1 As shown, it is a module structure diagram of the simulation process realized by the present invention. In the figure, the simulation process console is responsible for establishing a self-test platform, a module-level verification platform or a system-level verification platform. The simulation process console determines the simulation level according to user instructions, and generates a list of corresponding level verification files, paths and macro definitions; and then performs The working directory is converted, and the simulation is started; the verification ...

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Abstract

The invention discloses a method for improving functional verification efficiency of an embedded processor. The method is realized through a simulation flow control table and a verification platform. The simulation flow control table is in charge of setting up a self-testing platform and a module level verification platform or a system level verification platform, carrying out working directory conversion and starting simulation; the verification platform is in charge of generating random excitation and calling a compiler to carry out compiling, reference model operation and simulation result comparison on orders which are randomly generated.

Description

technical field [0001] The invention belongs to the technical field of embedded processors, in particular to a method for verifying functions of embedded processors. Background technique [0002] Fast time to market and minimal bug leaks have always been the pursuit of everyone, but a chip needs to go through a lot of links from the beginning of functional requirements to the launch of competition and testing. Synthesis, STA, post-imitation, mixed imitation and other links. According to data from authoritative organizations, if a bug leaks one more process, the cost will increase exponentially. Therefore, how to find bugs as early as possible and minimize bug leaks is the most important responsibility of verification engineers. Reduce the workload of follow-up links, improve development efficiency, and save development costs. [0003] Pre-imitation is the first step after coding is completed. The main task is to build a more realistic and complete scene to verify the corre...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/26
Inventor 唐疆斌
Owner CHIPSEA TECH SHENZHEN CO LTD
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