Rapid configuration and test method for programmable logic device in system programming

Abstract

The invention discloses a rapid configuration and test method for a programmable logic device in system programming. According to the method, ISP (in-system programmable) state machine configuration codes are acquired by one-time programming and four-time transcoding. The rapid configuration and test method includes the steps of conducting test configuration program development in a corresponding development environment of the programmable logic device to acquire original configuration codes; converting the original configuration codes into an SVF (serial vector format) file through a conversion tool; converting the SVF file into a PCF (portable compiled format) file; generating an ATP file by a C-language transcoding program; converting the ATP file into a Pattern file, and using an ATE (automatic test equipment) automatic test system for rapid configuration and test. The rapid configuration and test method for the programmable logic device in system programming has the advantages that the ISP state machine configuration codes can be generated automatically, and multi-time configuration and test operation can be conducted, so that test fault coverage rate is increased greatly, and the test problem of the programmable logic device is solved; the rapid configuration and test method is universal.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and relates to a configuration and testing method of a programmable logic device, in particular to a rapid configuration and testing method of in-system programming of a programmable logic device. Background technique [0002] Programmable logic devices include PROM, PAL, GAL, PLA, CPLD, FPGA, etc. They are mainly composed of programmable AND arrays, OR arrays, gate arrays, etc., and can realize certain logic functions through programming. [0003] To test a programmable logic device, it is necessary to conduct a structural analysis of the resources that may be contained within it, and go through a process of test configuration (TC) and vector implementation (TS) to configure it as a circuit with specific functions, and then from the application level Test the circuit and complete the function and parameter test of the circuit. [0004] In-System Programmable (In-System Programmable,...

AI Technical Summary

Problems solved by technology

The test of CPLD devices is often to use the download line to program first and then go to the test system for testing. Only one configuration-test process is performed. This method has low test coverage, or in the process of programming with the download line, logic analysis is used. It is very time-consuming and labor-intensive and easy to make mistakes; although the FPGA device test can be implemented in the system configuration and test through configuration methods such as slave serial or slave parallel, but for JTAG The test still needs to use the state machine method for configuration and verification

Images