Rapid configuration and test method for programmable logic device in system programming
A programming logic and rapid configuration technology, applied in the field of integrated circuits, can solve problems such as error-prone, low test coverage, time-consuming and labor-intensive, etc., to achieve the effect of improving efficiency and quality, and improving test fault coverage
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- Publication Date
- 2015-04-15
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The invention belongs to the technical field of integrated circuits, and relates to a configuration and testing method of a programmable logic device, in particular to a rapid configuration and testing method of in-system programming of a programmable logic device. Background technique
[0002] Programmable logic devices include PROM, PAL, GAL, PLA, CPLD, FPGA, etc. They are mainly composed of programmable AND arrays, OR arrays, gate arrays, etc., and can realize certain logic functions through programming.
[0003] To test a programmable logic device, it is necessary to conduct a structural analysis of the resources that may be contained within it, and go through a process of test configuration (TC) and vector implementation (TS) to configure it as a circuit with specific functions, and then from the application level Test the circuit and complete the function and parameter test of the circuit.
[0004] In-System Programmable (In-System Programmable,...
Examples
Embodiment 1
[0038] The present invention adopts the technical solution as a quick configuration and testing method for in-system programming of programmable logic devices, and the quick configuration and testing method obtains the configuration code of the ISP state machine through one programming and four transcoding processes;
[0039] The steps of the quick configuration and testing method are:
[0040] (1) Develop the test configuration program in the corresponding development environment of the programmable logic device, and obtain the original configuration code;
[0041] (2) Convert the original configuration code into an SVF file in serial vector format through a conversion tool; the conversion tools are: Xilinx's iMPACT tool, Altera's "Creat JAM, SVF, ISC" tool, Cypress's ISR tool, Lattice The company's ispVM tool.
[0042] (3) Convert SVF format files into PCF format files; the conversion tool is Svf2pcf transcoding program;
[0043] (4) Use the C language transcoding program ...