Rapid configuration and test method for programmable logic device in system programming

A programming logic and rapid configuration technology, applied in the field of integrated circuits, can solve problems such as error-prone, low test coverage, time-consuming and labor-intensive, etc., to achieve the effect of improving efficiency and quality, and improving test fault coverage

Inactive Publication Date: 2015-04-15

58TH RES INST OF CETC

8 Cites 19 Cited by

AI-Extracted Technical Summary

Problems solved by technology

The test of CPLD devices is often to use the download line to program first and then go to the test system for testing. Only one configuration-test process is performed. This method has low test coverage, or in the process of programming with the download line, logic analysis is used. It is very time-consu...

Abstract

The invention discloses a rapid configuration and test method for a programmable logic device in system programming. According to the method, ISP (in-system programmable) state machine configuration codes are acquired by one-time programming and four-time transcoding. The rapid configuration and test method includes the steps of conducting test configuration program development in a corresponding development environment of the programmable logic device to acquire original configuration codes; converting the original configuration codes into an SVF (serial vector format) file through a conversion tool; converting the SVF file into a PCF (portable compiled format) file; generating an ATP file by a C-language transcoding program; converting the ATP file into a Pattern file, and using an ATE (automatic test equipment) automatic test system for rapid configuration and test. The rapid configuration and test method for the programmable logic device in system programming has the advantages that the ISP state machine configuration codes can be generated automatically, and multi-time configuration and test operation can be conducted, so that test fault coverage rate is increased greatly, and the test problem of the programmable logic device is solved; the rapid configuration and test method is universal.

Application Domain

Electronic circuit testingSoftware testing/debugging

Technology Topic

EngineeringDevelopment environment +8

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Examples

Experimental program(1)
Effect test(1)

Example Embodiment

[0037] Example 1

[0038] The present invention adopts a technical solution for a rapid configuration and test method of programmable logic device in-system programming, and the rapid configuration and test method obtains the ISP state machine configuration code through a process of four transcoding of programming once;

[0039] The steps of the quick configuration and test method are:

[0040] (1) Develop the test configuration program in the corresponding development environment of the programmable logic device to obtain the original configuration code;

[0041] (2) Convert the original configuration code into a serial vector format SVF file through a conversion tool; the conversion tools are: Xilinx's iMPACT tool, Altera's "Creat JAM, SVF, ISC" tool, Cypress's ISR tool, Lattice The company's ispVM tool.

[0042] (3) Convert SVF format files to PCF format files; the conversion tool is Svf2pcf transcoding program;

[0043] (4) Use the C language transcoding program to extract the valid data in the PCF format file and directly generate the ATP format file; the conversion tool is the Pcf2atp transcoding program;

[0044] (5) Convert the ATP format to the Pattern file required by the test system, and use the ATE automatic test system to quickly configure and test the programmable logic device in the system programming.

[0045] In this method, the programmable logic devices of different companies use different development environments to develop test configuration programs. Xilinx's programmable logic devices use the ISE development environment to develop test configuration programs to obtain test configuration programs in .bit, .bin, and .mcs formats; Altera's programmable logic devices use Quartus development environment to develop test configuration programs to obtain .pof , .Sof format test configuration program; Lattice company’s programmable logic device uses ispLEVER development environment for test configuration program development to obtain .jed format test configuration program; Cypress company’s programmable logic device uses Warp development environment for test configuration program development Obtain the test configuration program in .jed format.

[0046] This method uses the test configuration program to automatically transcode to generate the ISP configuration code, and the ATE automatic test system is directly configured in the system quickly; it does not use manual collection to make the configuration code and the method of using the download line and the programmer to configure. The traditional methods of manually collecting and making configuration codes and using download lines and programmers for configuration have low test coverage, time-consuming, labor-intensive, and error-prone methods, which are not conducive to improving the rapid configuration and test operations of programmable logic devices.

[0047] Programmable logic devices include PROM, PAL, GAL, PLA, CPLD, FPGA and other programmable logic devices from companies such as Xilinx, Altera, Lattice, Cypress, etc.

[0048] ATE automatic test system includes: J750EX and/or Ultra-FLEX test system from Teradyne, USA. Choose one of the above two automatic detection systems as the ATE automatic test system according to the product characteristics of the programmable logic device being tested;

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Classification and recommendation of technical efficacy words

Improve efficiency and quality

Rapid configuration and test method for programmable logic device in system programming

A programming logic and rapid configuration technology, applied in the field of integrated circuits, can solve problems such as error-prone, low test coverage, time-consuming and labor-intensive, etc., to achieve the effect of improving efficiency and quality, and improving test fault coverage

AI-Extracted Technical Summary

Problems solved by technology

Abstract

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Examples

Example Embodiment

PUM

Description & Claims & Application Information

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