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FPGA (field programmable gate array) based time-digital converter

A technology of time digital and converter, which is applied in the direction of electrical unknown time interval measurement, devices and instruments for measuring time interval, and can solve problems such as measurement error of measurement nodes

Active Publication Date: 2015-05-13
UNIV OF SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The delay width of each delay unit has non-uniformity, and each measurement node has measurement error

Method used

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  • FPGA (field programmable gate array) based time-digital converter
  • FPGA (field programmable gate array) based time-digital converter
  • FPGA (field programmable gate array) based time-digital converter

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Embodiment Construction

[0050] figure 1 It is a structural schematic diagram of the FPGA-based time-to-digital converter provided by the present invention. Such as figure 1 As shown, it includes a coarse clock counter, a pulse signal generator, a signal delay chain, a flip-flop array, a connection network, a signal change edge search and encoding circuit, and a time stamp output circuit.

[0051] The coarse clock counter is driven by the system clock signal and is used to generate a coarse time stamp of the signal under test.

[0052] The pulse signal generator is externally triggered, which is used to generate a pulse with a changing edge under the trigger of the signal under test and feed it into the signal delay chain for transmission. The changing edge may be a rising edge or a falling edge.

[0053] The signal delay chain is used to delay the transmission of the signal under test. It is composed of multiple delay units and has taps at the front end of each delay unit. Therefore, the signal de...

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Abstract

The invention discloses an FPGA (field programmable gate array) based time-digital converter comprising a pulse signal generator, a multi-tab signal delay chain, a trigger array, a connection network, a signal change edge searching and encoding circuit and a time stamp output circuit. The pulse signal generator is triggered by a measured signal to generate a falling edge and feeds the falling edge into a signal delay chain. The trigger array is controlled by a system clock to latch tap states of the signal delay chain and transmit the tap states to the connection network. The connection network resorts and extracts the latched taps according to distribution of delay width of delay units of the signal delay chain measured in advance and transmits the tap states to the signal change edge searching and encoding circuit. The FPGA based time-digital converter has the advantages that the influence of the 0 delay unit on the signal delay chain and nonlinear error can be maximally eliminated, bubbling in thermometer code under the tap state is decreased, and performance indexes, namely measuring precision, measuring dead time and resource usage, are reasonably balanced, and a high-performance TDC (time to digital) measuring system is achieved.

Description

technical field [0001] The invention belongs to the field of digital measurement of time, in particular to an FPGA-based time-to-digital converter. Background technique [0002] Time measurement refers to measuring the moment when an event occurs, or measuring the time interval between two events. Time measurement technology has important applications in many fields, such as high-energy physics experiment research, nuclear medical imaging, military and civilian radar, and laser ranging and other fields require high-precision time measurement technology. A time-to-digital converter (TDC: Time-Digital-Convertor) is a functional device that converts time into digital quantities to record the moment when an event occurs. For the measurement of the time interval between two events, generally two TDCs can be used to measure the occurrence moments of the two events respectively, and the difference between the two occurrence moments is the time interval between the two events. At ...

Claims

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Application Information

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IPC IPC(8): G04F10/04G04F10/00
Inventor 王永纲刘冲
Owner UNIV OF SCI & TECH OF CHINA
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