Method for manufacturing semiconductor package

Abstract

The invention provides a method for manufacturing a semiconductor package, wherein a packaging structure comprising a carrier, a semiconductor assembly formed on the carrier, and a packaging material for packaging the semiconductor assembly is provided. Meanwhile, a bearing structure is combined with the packaging structure on the packaging material. After that, the carrier is removed. Based on the above structure of the bearing structure, the stress applied on the packaging material is balanced, so that the subsequent wiring operation is smoother.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor package, in particular to a method for manufacturing a semiconductor package with a fan-out (Fan-out) circuit structure and anti-warping. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of semiconductor packages, a wafer level packaging (Wafer Level Packaging, WLP) technology has been developed. [0003] like Figure 1A to Figure 1D , is a schematic cross-sectional view of a conventional wafer-level semiconductor package 1 manufacturing method. [0004] like Figure 1A As shown, a thermal release tape 11 is formed on a carrier 10 . [0005] Next, place a plurality of semiconductor components 12 on the thermal release adhesive layer 11, these semiconductor components 12 have opposite a...

AI Technical Summary

Problems solved by technology

[0010] However, in the existing manufacturing method of the semiconductor package 1, since the panel size of the carrier 10 is too large, when the carrier 10 is removed, the encapsulant 13 will warp too much (warpage) ( like Figure 1C The encapsulant 13' shown has a height difference h of 15mm), which makes the subsequent RDL unable to work, that is, the alignment between the redistribution structure 14 and the electrode pad 120 of the semiconductor component 12 will be offset. When the size of the carrier 10 is larger, the position tolerance between the semiconductor components 12 is also increased, and when the offset tolerance is too large, the wiring redistribution structure 14 cannot be connected to the electrode pad 120

Therefore, the electrical connection between the redistribution structure 14 and the semiconductor device 12 is greatly affected, resulting in problems such as low yield rate and poor product reliability.

Images